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* ilo: add a new disassemblerChia-I Wu2014-09-113-4444/+1352
| | | | | | | | The old disassembler was modified from i965's. It is as much work as doing a new one to keep it up-to-date, which also requires copying more headers over. The outputs of this new disassembler should match i965's as closely as possible.
* ilo: update genhw headersChia-I Wu2014-09-1111-247/+203
| | | | | | | | Add some new registers and some tweaks. The changes that affect ilo are GEN6_REG_HS_INVOCATION_COUNT -> GEN7_REG_HS_INVOCATION_COUNT GEN6_REG_DS_INVOCATION_COUNT -> GEN7_REG_DS_INVOCATION_COUNT GEN6_COND_NORMAL -> GEN6_COND_NONE
* radeonsi: Simplify si_dma_copy_tile functionMichel Dänzer2014-09-111-62/+41
| | | | | | No functional change intended. Reviewed-by: Marek Olšák <[email protected]>
* vc4: Add support for shadow samplers.Eric Anholt2014-09-091-3/+58
| | | | | | | This doesn't quite make depth-tex-compare work, presumably because we're not hitting equality with itof(sample) * 1.0/0xffffff in the 0xffffff case. arb_fragment_program_shadow tests pass, though, as well as a bunch of other shadow-related stuff.
* vc4: Add support for texture swizzles.Eric Anholt2014-09-091-1/+8
| | | | Fixes depth-tex-modes.
* vc4: Move the texture format into a struct.Eric Anholt2014-09-091-3/+5
| | | | I'm going to be putting some bitfields into the struct as well.
* vc4: Add support for depth texturing.Eric Anholt2014-09-091-3/+13
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* vc4: Expose r4 to register allocation.Eric Anholt2014-09-094-23/+49
| | | | | | | | We potentially need to be careful that use of a value stored in r4 isn't copy-propagated (or something) across another r4 write. That doesn't appear to happen currently, and this makes the dataflow more obvious. It also opens up not unpacking the r4 value, which will be useful for depth textures.
* vc4: Drop pointless raddr conflict handling on SF.Eric Anholt2014-09-091-1/+0
| | | | SF doesn't have a src[1].
* vc4: The r4_count is supposed to be how many writes, not reads.Eric Anholt2014-09-091-1/+1
| | | | It's part of the key so that you can tell which r4 value is being read.
* r600g,radeonsi: Set RADEON_GEM_NO_CPU_ACCESS flag for tiled BOsMichel Dänzer2014-09-101-0/+1
| | | | | | | This lets the kernel know that such BOs can be pinned outside of the CPU accessible part of VRAM. Reviewed-by: Marek Olšák <[email protected]>
* freedreno/a3xx: enable hw primitive-restartRob Clark2014-09-094-9/+20
| | | | | | | | | | Since software primitive-restart emulation is going to be removed (and anyways, mostly seemed to be crash prone in combination with u_primconvert and oddball scenarios (like PIPE_PRIM_POLYGON with only a single vertex), might as well do it in hardware (which fortunately didn't turn out to be too hard to figure out). Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-09-094-13/+18
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix potential segfault in RARob Clark2014-09-091-2/+6
| | | | | | | | | | | | | | | | | | | | | | Triggered by shaders like: FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL OUT[0], COLOR DCL CONST[0] DCL TEMP[0..2], LOCAL 0: IF CONST[0].xxxx :0 1: MOV TEMP[0], TEMP[1] 2: ELSE :0 3: MOV TEMP[0], TEMP[2] 4: ENDIF 5: MOV OUT[0], TEMP[0] 6: END not really a sane shader, although driver segfaulting is probably not the appropriate response. Signed-off-by: Rob Clark <[email protected]>
* freedreno: don't overflow cmdstream buffer so muchRob Clark2014-09-091-0/+15
| | | | | | | | | | | | | | We currently aren't too clever about dealing with running out of cmdstream buffer space. Since we use a single buffer for both drawing and tiling commands, we need to ensure there is enough space at the tail of the cmdstream buffer to fit the tiling commands. Until we get more clever, the easy solution is a threshold to trigger flushing rendering even if the application does not trigger flush (swap, changing render target, etc). This way we at least don't crash for apps that do several thousand draw calls (like some piglit tests do). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add no-copy-propagate fallback stepRob Clark2014-09-093-11/+21
| | | | | | | | | | | Most of the things the new compiler still has trouble with basically amount to cp stage removing too many copies. But without the cp stage, the shaders the new compiler produces are still better (perf and correctness) than the old compiler. So a simple thing to do until I have more time to work on it is first trying falling back to new compiler without cp, before finally falling back to old compiler. Signed-off-by: Rob Clark <[email protected]>
* ilo: add ilo_builder.h to the sources listEmil Velikov2014-09-091-0/+1
| | | | Signed-off-by: Emil Velikov <[email protected]>
* vc4: Fix segfaults when rendering with no color render target.Eric Anholt2014-09-092-8/+18
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* vc4: Fill out the stencil clear field.Eric Anholt2014-09-093-1/+5
| | | | | | The rest of stencil handling isn't done yet, but it documents an extra cl_u8(0) and helps make it obvious why we don't need to format clear_depth the same way the depth/stencil buffer is formatted.
* vc4: Flip around the depth/stencil fields.Eric Anholt2014-09-093-5/+9
| | | | | After implementing depth stores, it looks like this is the way things actually are, according to hiz-depth-read-fbo-d24-s0's probes.
* vc4: Add support for loading/storing the depth buffer.Eric Anholt2014-09-092-7/+62
| | | | | | For now it still requires the color buffer to be present -- we're relying on the store of color buffer contents to end the frame, and we have to do something with color buffers in the rendering config packet.
* vc4: Don't forget to do initial tile clearing for depth/stencil.Eric Anholt2014-09-091-1/+6
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* vc4: Ignore non-address bits of the offset for load/store.Eric Anholt2014-09-091-1/+1
| | | | | These only get used for full buffer dumps, which we don't support yet anyway.
* vc4: Add a debug flag for flushing after every draw.Eric Anholt2014-09-093-0/+6
| | | | | It was useful on i965, but it's even more useful for debugging tiled renderers.
* vc4: Add missing null terminator to the debug options list.Eric Anholt2014-09-091-0/+1
| | | | | So far, apparently there's been some NULL laying at the address just after the options anyway, but the next commit changed that.
* ilo: remove unused ilo_cp functionsChia-I Wu2014-09-092-146/+0
| | | | | | | | | | | | | Remove ilo_cp_begin() ilo_cp_steal() ilo_cp_write() ilo_cp_write_multi() ilo_cp_write_bo() ilo_cp_end() ilo_cp_steal_ptr() ilo_cp_assert_no_implicit_flush()
* ilo: convert GPE GEN6 command functions to use ilo_builderChia-I Wu2014-09-094-764/+730
| | | | | | | Similar to the changes to GEN7 command functions, but to GEN6 this time. As every GPE function has been converted, remove ilo_cp_assert_no_implicit_flush() calls.
* ilo: convert GPE GEN7 command functions to use ilo_builderChia-I Wu2014-09-094-517/+479
| | | | | | | | | | Make these changes ilo_cp_begin() -> ilo_builder_batch_pointer() ilo_cp_write() -> direct memory set ilo_cp_write_bo() -> ilo_builder_batch_reloc() and use this chance to drop the "_emit_" infix.
* ilo: convert GPE state functions to use ilo_builderChia-I Wu2014-09-094-154/+129
| | | | | | | | | Make these changes ilo_cp_steal_ptr() and memcpy() -> ilo_builder_state_write() ilo_cp_steal_ptr() -> ilo_builder_state_pointer() and use this chance to drop the "_emit_" infix.
* ilo: convert GPE surface functions to use ilo_builderChia-I Wu2014-09-092-56/+36
| | | | | | | | | | Make these changes ilo_cp_steal_ptr() and memcpy() -> ilo_builder_surface_write() ilo_cp_steal() and ilo_cp_write() -> ilo_builder_surface_write() ilo_cp_write_bo() -> ilo_builder_surface_reloc() and use this chance to drop the "_emit_" infix.
* ilo: convert BLT to use ilo_builderChia-I Wu2014-09-091-119/+122
| | | | | | | | | | | Make these changes ilo_cp_begin() -> ilo_builder_batch_pointer() ilo_cp_write() -> direct memory set ilo_cp_write_bo() -> ilo_builder_batch_reloc() and make sure there is no implicit flush. Use this chance to drop the "_emit_" infix.
* ilo: use ilo_builder for kernels and STATE_BASE_ADDRESSChia-I Wu2014-09-099-201/+61
| | | | | | Remove instruction buffer management from ilo_3d and adapt ilo_shader_cache to upload kernels to ilo_builder. To be able to do that, we also let ilo_builder manage STATE_BASE_ADDRESS.
* ilo: make ilo_cp based on ilo_builderChia-I Wu2014-09-0916-979/+114
| | | | | This makes ilo_cp use the builder to manage batch buffers, and use ilo_builder_decode() to replace ilo_3d_pipeline_dump().
* ilo: add a builder for building BOs for submissionChia-I Wu2014-09-094-0/+1641
| | | | | | | | | | | Comparing to how we manage batch and instruction buffers, the new builder - does not flush - manages both types of buffers - manages STATE_BASE_ADDRESS - uploads kernels using unsynchronized mapping - has its own decoder for the buffers - provides more helpers
* ilo: make toy_compiler_disassemble() more usefulChia-I Wu2014-09-095-9/+11
| | | | | | Do not require a toy_compiler so that it can be used in other places, such as state dumping. Add a bool to control whether the raw instruction words are shown.
* nv50/ir: accomodate all file types, there are now more than 8Ilia Mirkin2014-09-081-2/+2
| | | | | | Reported by Coverity Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: uses was always null at that point in the codeIlia Mirkin2014-09-081-7/+1
| | | | | | Reported by Coverity Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: avoid array overrun when checking for supported modsIlia Mirkin2014-09-082-2/+2
| | | | | | | Reported by Coverity Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.2 10.3" <[email protected]>
* nouveau: buffer can never be nullIlia Mirkin2014-09-081-2/+0
| | | | | | Reported by Coverity Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: insn can never be nullIlia Mirkin2014-09-081-1/+1
| | | | | | Reported by Coverity. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: size is a uint16_t, remove unnecessary assertionIlia Mirkin2014-09-081-1/+0
| | | | | | Reported by Coverity. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: avoid null deref of screen when collecting statsIlia Mirkin2014-09-081-1/+1
| | | | | | Reported by Coverity Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: use 64-bit math when scaling the query resultsIlia Mirkin2014-09-081-4/+4
| | | | | | Reported by Coverity. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: clarify recursion fix to finding first tex usesChristoph Bumiller2014-09-051-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a simple shader for reproducing the case mentioned: FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL TEMP[0..1], LOCAL IMM[0] FLT32 { 0.0000, -1.0000, 1.0000, 0.0000} 0: MOV TEMP[0].x, CONST[0].wwww 1: MOV TEMP[1].x, CONST[0].wwww 2: BGNLOOP 3: IF TEMP[0].xxxx 4: BRK 5: ENDIF 6: ADD TEMP[0].x, TEMP[0], IMM[0].zzzz 7: IF CONST[0].xxxx 8: TEX TEMP[1].x, CONST[0], SAMP[0], 2D 9: ENDIF 10: IF CONST[0].zzzz 11: MOV TEMP[1].x, CONST[0].zzzz 12: ENDIF 13: ENDLOOP 14: MOV OUT[0], TEMP[1].xxxx 15: END Cc: "10.2 10.3" <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir/util: fix BitSet issuesChristoph Bumiller2014-09-053-3/+10
| | | | | | | | | | | | | BitSet::allocate() is being used with the expectation that it would leave the bitfield untouched if its size hasn't changed, however, the function always zeroed the last word, which led to obscure bugs with live set computation. This also fixes BitSet::resize(), which was broken, but luckily not being used. Cc: "10.2 10.3" <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: remove nvc0_push, replaced with nvc0_vbo_translateIlia Mirkin2014-09-052-410/+0
| | | | | | Fixes build. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50,nvc0: get rid of draw module supportIlia Mirkin2014-09-057-224/+0
| | | | | | | This hasn't been enabled in a long time and is completely stale and unnecessary. Remove, esp since it doesn't build. Signed-off-by: Ilia Mirkin <[email protected]>
* gallium/vc4: ship all files in the tarballEmil Velikov2014-09-051-1/+13
| | | | | | | | | - include all headers in Makefile.sources Cc: Eric Anholt <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Acked-by: Matt Turner <[email protected]>
* gallium/trace: ship all files in the tarballEmil Velikov2014-09-052-1/+12
| | | | | | | | - include all headers in Makefile.sources - bundle the scons buildscript, README and trace.xsl Signed-off-by: Emil Velikov <[email protected]> Acked-by: Matt Turner <[email protected]>
* gallium/svga: ship all files in the tarballEmil Velikov2014-09-052-12/+62
| | | | | | | | | | - include all headers in Makefile.sources - sort the list(s) - bundle the android & scons buildscript - include the headers' README & svga_dump.py Signed-off-by: Emil Velikov <[email protected]> Acked-by: Matt Turner <[email protected]>
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