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* winsys/amdgpu: explicitly declare whether buffer_map is permanent or notNicolai Hähnle2018-11-2814-28/+67
* virgl: Don't try handling server fences when they are not supportedGert Wollny2018-11-281-2/+4
* v3d: Add renderonly support.Eric Anholt2018-11-274-4/+68
* freedreno: implements get_sample_positionHyunjun Ko2018-11-271-0/+45
* freedreno/a3xx: also set FSSUPERTHREADENABLERob Clark2018-11-271-0/+1
* freedreno: use MSM_BO_SCANOUT with scanout buffersJonathan Marek2018-11-271-1/+3
* freedreno: use GENERIC instead of TEXCOORD for blit programJonathan Marek2018-11-271-1/+1
* freedreno: a2xx texture updateJonathan Marek2018-11-279-20/+212
* freedreno/a2xx: Compute depth base in gmem correctlyJonathan Marek2018-11-271-5/+7
* freedreno/a2xx: set VIZ_QUERY_ID on a20xJonathan Marek2018-11-271-0/+5
* freedreno: add missing a20x idsJonathan Marek2018-11-271-0/+2
* freedreno/a2xx: fix POINT_MINMAX_MAX overflowJonathan Marek2018-11-271-1/+1
* freedreno: a2xx: fd2_draw updateJonathan Marek2018-11-276-20/+114
* freedreno: update generated headersRob Clark2018-11-277-39/+287
* freedreno/a6xx: set guardband clipRob Clark2018-11-274-7/+57
* freedreno/a6xx: disable LRZ for z32Rob Clark2018-11-271-1/+13
* freedreno/a6xx: Clear gmem buffers at flush timeKristian H. Kristensen2018-11-274-178/+180
* freedreno/a6xx: Move resolve blits to an IBKristian H. Kristensen2018-11-273-8/+29
* freedreno/a6xx: Move restore blits to IBKristian H. Kristensen2018-11-273-19/+49
* freedreno: move ir3 to common locationRob Clark2018-11-2740-13732/+37
* freedreno/ir3: remove u_inlines usageRob Clark2018-11-271-10/+10
* freedreno/ir3: split up ir3_shaderRob Clark2018-11-2714-667/+766
* freedreno/ir3: remove pipe_stream_output_info dependencyRob Clark2018-11-278-17/+68
* freedreno/ir3: some header file cleanupRob Clark2018-11-2711-26/+24
* freedreno/ir3: use env_var_as_unsigned()Rob Clark2018-11-272-14/+2
* freedreno/ir3: move disasm and optmsgs debug flagsRob Clark2018-11-279-22/+25
* freedreno: FD_SHADER_DEBUG -> IR3_SHADER_DEBUGRob Clark2018-11-274-33/+34
* freedreno: remove shader_stage_name()Rob Clark2018-11-273-21/+3
* freedreno: shader_t -> gl_shader_stageRob Clark2018-11-2722-143/+121
* freedreno/ir3: standalone compiler updatesRob Clark2018-11-271-6/+27
* freedreno: move drm to common locationRob Clark2018-11-2720-3717/+12
* freedreno/drm: remove dependency on gallium driverRob Clark2018-11-271-2/+11
* nv50/ir: remove dnz flag when converting MAD to ADD due to optimizationsIlia Mirkin2018-11-241-0/+3
* virgl: add assert and missing function parameterRobert Foss2018-11-211-1/+4
* r600: clean up the GS ring buffers when the context is destroyedGert Wollny2018-11-211-0/+6
* radeonsi: go back to using bottom-of-pipe for beginning of TIME_ELAPSEDMarek Olšák2018-11-201-11/+4
* radeonsi: don't send data after write-confirm with BOTTOM_OF_PIPE_TSMarek Olšák2018-11-203-9/+5
* meson: Add tests to suitesDylan Baker2018-11-202-2/+4
* nir: Make nir_lower_clip_vs optionally work with variables.Kenneth Graunke2018-11-192-2/+3
* etnaviv: use dummy RT buffer when rendering without color bufferLucas Stach2018-11-193-2/+19
* radeonsi: fix an out-of-bounds read reported by ASANNicolai Hähnle2018-11-191-0/+4
* r600: Only set context streamout strides info from the shader that has outputsGert Wollny2018-11-191-3/+9
* virgl: Clean up fences commitRobert Foss2018-11-181-1/+1
* nv50/ir/ra: enforce max register requirement, and change spill orderIlia Mirkin2018-11-164-16/+26
* nv50/ir/ra: improve condition for short regs, unify with cond for 16-bitIlia Mirkin2018-11-161-7/+7
* nv50/ir: delete MINMAX instruction that is no longer in the BBIlia Mirkin2018-11-161-1/+1
* virgl: native fence fd supportRobert Foss2018-11-163-10/+62
* vc4: Don't return a vc4 BO handle on a renderonly screen.Eric Anholt2018-11-151-2/+4
* vc4: Make sure we make ro scanout resources for create_with_modifiers.Eric Anholt2018-11-151-1/+9
* v3d: Fix double-swapping of R/B on V3D 4.1Eric Anholt2018-11-151-2/+3
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