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* r600g: increase array base for exported parametersDave Airlie2014-02-051-0/+3
* r600g: initialise the geom shader loop registers.Dave Airlie2014-02-051-0/+2
* r600g: emit NOPs at end of shaders in more casesDave Airlie2014-02-051-2/+5
* r600g: don't enable SB for geom shadersDave Airlie2014-02-051-0/+3
* r600g/sb: add MEM_RING supportDave Airlie2014-02-054-5/+8
* r600g: don't fail if we can't map VS->GS ring entriesDave Airlie2014-02-051-4/+3
* r600g: initial support for geometry shaders on evergreen (v2)Vadim Girlin2014-02-0515-206/+909
* r600g: add hw register definitions for GS block setupVadim Girlin2014-02-052-6/+75
* r600g: defer shader variant selection and depending state updatesVadim Girlin2014-02-053-69/+57
* r600g/bc: add support for indexed memory writes.Dave Airlie2014-02-053-4/+12
* r600g: move barrier and end_of_program bits from output to cf struct (v2)Vadim Girlin2014-02-054-30/+34
* r600g: split streamout emit code into a separate functionDave Airlie2014-02-051-103/+110
* r600g,radeonsi: skip unnecessary buffer_is_busy call, add a commentMarek Olšák2014-02-041-1/+5
* r600g,radeonsi: skip busy-checking for DISCARD_RANGE if it has been done alreadyMarek Olšák2014-02-041-0/+4
* r600g,radeonsi: treat DYNAMIC and STREAM usage as STAGINGMarek Olšák2014-02-041-7/+3
* gallium: remove PIPE_CAP_MAX_COMBINED_SAMPLERSMarek Olšák2014-02-0412-29/+0
* radeon/uvd: fix feedback buffer handling v2Christian König2014-02-041-12/+28
* freedreno: enabling binning and opt by defaultRob Clark2014-02-033-16/+11
* freedreno/a3xx/compiler: new compilerRob Clark2014-02-0317-209/+2777
* freedreno/a3xx/compiler: split out old compilerRob Clark2014-02-036-1/+1531
* freedreno/a3xx/compiler: prepare for new compilerRob Clark2014-02-039-146/+308
* freedreno/a3xx: remove useless reg tracking in disasm-a3xxRob Clark2014-02-031-174/+0
* svga: check shader size against max command buffer sizeBrian Paul2014-02-032-12/+49
* svga: refactor some shader codeBrian Paul2014-02-0311-76/+171
* freedreno: better manage our WFI'sRob Clark2014-02-017-24/+36
* freedreno/a3xx: add logicopRob Clark2014-02-013-6/+27
* freedreno/a3xx: handle frag z writeRob Clark2014-02-017-25/+53
* freedreno: resync generated headersRob Clark2014-02-014-9/+39
* freedreno/a3xx: fix const confusionRob Clark2014-02-012-9/+9
* freedreno/a3xx/compiler: compiler cleanupsRob Clark2014-02-017-145/+198
* freedreno/compiler/a3xx: remove lowered instructionsRob Clark2014-02-011-354/+0
* freedreno: add tgsi lowering passRob Clark2014-02-014-2/+1229
* freedreno/a3xx/compiler: add CLAMPRob Clark2014-02-011-7/+24
* freedreno/a3xx/compiler: various fixesRob Clark2014-02-011-14/+34
* freedreno: ctx should hold ref to devRob Clark2014-02-016-2/+8
* freedreno: add prims-emitted driver queryRob Clark2014-02-011-0/+1
* llvmpipe: fix denorm handling for r11g11b10_float format when blendingRoland Scheidegger2014-01-311-2/+15
* r600g: Removed unnecessary positivity check for unsigned int variable.Siavash Eliasi2014-01-311-1/+1
* freedreno: Set PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT to 64Ian Romanick2014-01-291-0/+3
* ilo: Set PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT to 64Siavash Eliasi2014-01-291-1/+1
* svga: Set PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT to 64Siavash Eliasi2014-01-291-1/+2
* i915g: Set PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT to 64Siavash Eliasi2014-01-291-1/+3
* i915g: Use alignment of 64 instead of 16 for buffer allocationSiavash Eliasi2014-01-291-1/+1
* llvmpipe: Set PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT to 64Siavash Eliasi2014-01-291-1/+2
* llvmpipe: Use alignment of 64 instead of 16 for buffer allocationSiavash Eliasi2014-01-291-3/+3
* softpipe: Set PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT to 64Siavash Eliasi2014-01-291-1/+2
* softpipe: Use alignment of 64 instead of 16 for buffer allocationSiavash Eliasi2014-01-291-2/+2
* i915g: support more PIPE_CAPsStéphane Marchesin2014-01-281-3/+6
* radeonsi: Put GS ring buffer descriptors with streamout buffer descriptorsMichel Dänzer2014-01-295-84/+115
* radeonsi: Enable OpenGL 3.3Michel Dänzer2014-01-291-3/+5
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