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* radeonsi:optimizing SET_CONTEXT_REG for shaders TessellationSonny Jiang2018-10-054-5/+26
* radeonsi:optimizing SET_CONTEXT_REG for shaders PSSonny Jiang2018-10-053-14/+60
* radeonsi:optimizing SET_CONTEXT_REG for shaders VSSonny Jiang2018-10-053-33/+77
* radeonsi:optimizing SET_CONTEXT_REG for shaders GSSonny Jiang2018-10-054-24/+154
* radeonsi: optimize and allow reg > 31 in radeon_opt_set_context_reg functionsMarek Olšák2018-10-051-22/+12
* radeonsi: optimizing SET_CONTEXT_REG for shaders ESSonny Jiang2018-10-055-10/+37
* etnaviv: Use write combine instead of unached mappings for shader boGuido Günther2018-10-041-1/+1
* freedreno: add the a6xx sources to the Android buildEmil Velikov2018-10-031-0/+1
* r600: use build-id when available for disk cacheTimothy Arceri2018-10-031-7/+7
* nouveau: use build-id when available for disk cacheTimothy Arceri2018-10-031-7/+7
* radeonsi: use build-id when available for disk cacheTimothy Arceri2018-10-031-12/+9
* radeonsi: avoid sending GS_EMIT in shaders without outputsJózef Kucia2018-10-021-3/+6
* radeonsi: initialize ac_gpu_info::name when using SI_FORCE_FAMILYMarek Olšák2018-10-021-0/+1
* radeonsi: don't set the VS prolog key for the blit VSMarek Olšák2018-10-021-1/+2
* freedreno/a6xx: hwbinningRob Clark2018-10-028-105/+159
* freedreno: update generated headersRob Clark2018-10-027-41/+52
* radeonsi: add a workaround for bitfield_extract when count is 0Timothy Arceri2018-10-021-11/+30
* freedreno/a6xx: Build up draw dword0 outside visibilty if statementKristian H. Kristensen2018-09-271-17/+18
* freedreno/a6xx: Simplify draw_emit() branches a bitKristian H. Kristensen2018-09-271-16/+8
* freedreno/a6xx: Copy OUT_RING() part into each branch of the index ifKristian H. Kristensen2018-09-271-17/+29
* freedreno/a6xx: Split fd6_draw_emit into direct and indirect pathsKristian H. Kristensen2018-09-271-36/+46
* freedreno/a6xx: Inline fd6_draw()Kristian H. Kristensen2018-09-271-31/+17
* freedreno/a6xx: Move emit_marker and wfi to draw_impl()Kristian H. Kristensen2018-09-271-17/+12
* freedreno/a6xx: Move inline functions out of fd6_draw.hKristian H. Kristensen2018-09-273-108/+110
* freedreno: fix a typo in launch_gridHyunjun Ko2018-09-271-1/+1
* freedreno/ir3: fix the param order of cmpxchgHyunjun Ko2018-09-271-2/+2
* freedreno/a6xx: fix shaders w/ >= 24 regsRob Clark2018-09-271-1/+1
* freedreno/a6xx: fix gl_FragCoord.wRob Clark2018-09-271-2/+6
* freedreno: handle invalidated buffers harderRob Clark2018-09-278-7/+39
* freedreno/a6xx: fix constlenRob Clark2018-09-271-7/+6
* freedreno: fix inorder rendering caseRob Clark2018-09-271-6/+7
* freedreno/a6xx: backface stencil stateRob Clark2018-09-272-2/+4
* freedreno/a6xx: fix gpu crash with separate-stencilRob Clark2018-09-271-1/+1
* freedreno/a6xx: fix MRT configRob Clark2018-09-271-7/+7
* freedreno: fix potential hang when destroying batchRob Clark2018-09-271-1/+1
* freedreno: fix corrupted fb stateRob Clark2018-09-272-2/+5
* freedreno: simplify pctx->clear()Rob Clark2018-09-276-74/+11
* freedreno: fix FD_MESA_DEBUG=flushRob Clark2018-09-272-2/+8
* freedreno: fix scissor state emitRob Clark2018-09-274-4/+8
* freedreno: update generated headersRob Clark2018-09-278-340/+1089
* radeonsi: NaN should pass kill_ifAxel Davy2018-09-251-1/+2
* radeon/uvd: use bitstream coded number for symbols of Huffman tablesLeo Liu2018-09-241-4/+14
* nv50/ir: fix link-time build failureRhys Perry2018-09-231-1/+1
* nvc0: fix bindless multisampled images on Maxwell+Rhys Perry2018-09-223-5/+45
* nvc0: warn about changing NVC0_CB_AUX_MP_INFO and NVC0_CB_AUX_DRAW_INFORhys Perry2018-09-221-2/+6
* nvc0: Update counter reading shaders to new NVC0_CB_AUX_MP_INFORhys Perry2018-09-221-18/+18
* vc4: Remove dead i == 0 code from the cos() implementation.Eric Anholt2018-09-211-6/+3
* vc4: Fix sin(0.0) and cos(0.0) accuracy to fix SDL rendering rotation.Eric Anholt2018-09-211-26/+40
* svga: fix uninitialized fields in DefineDepthStencilView/DefineStreamOutputCharmaine Lee2018-09-201-0/+9
* r300g: add PIPE_SHADER_CAP_SCALAR_ISA switch case to silence warningBrian Paul2018-09-201-0/+4
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