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* freedreno: update generated headersRob Clark2018-08-179-27/+32
* freedreno/a6xx: fix srgbRob Clark2018-08-171-7/+13
* freedreno: fix dEQP-GLES3.functional.fence_sync.*Rob Clark2018-08-171-0/+4
* freedreno: Add a6xx backendKristian H. Kristensen2018-08-1638-17/+6368
* freedreno: update generated headersRob Clark2018-08-167-66/+4928
* freedreno: Fix warningsKristian H. Kristensen2018-08-165-15/+9
* svga: simplify Mesa version stringEric Engestrom2018-08-161-1/+1
* bin: always define MESA_GIT_SHA1 to make it directly usable in codeEric Engestrom2018-08-161-5/+1
* virgl: report actual max-texture sizesErik Faye-Lund2018-08-152-0/+10
* virgl: do not use SP_MAX_TEXTURE_*_LEVELS definesErik Faye-Lund2018-08-151-7/+3
* radv: disable the auto-waitcnt-before-barrier LLVM optionSamuel Pitoiset2018-08-151-0/+1
* radeonsi: enable 1 missing PS_SU perf counter on PolarisMarek Olšák2018-08-141-1/+1
* radeonsi: use radeon_info::nameMarek Olšák2018-08-143-40/+12
* radeonsi: split si_clear_buffer to remove enum si_methodMarek Olšák2018-08-146-53/+60
* radeonsi: replace CP_DMA_USE_L2 with enum si_cache_policyMarek Olšák2018-08-142-26/+41
* radeonsi: declare coher in si_copy_bufferMarek Olšák2018-08-141-8/+7
* radeonsi: make PFP_SYNC_ME an explicit CP DMA flagMarek Olšák2018-08-141-17/+25
* radeonsi: don't use emit_data->args in load_emitMarek Olšák2018-08-141-94/+37
* radeonsi: don't use emit_data->args in store_emitMarek Olšák2018-08-141-92/+71
* radeonsi: don't use emit_data->args in atomic_emitMarek Olšák2018-08-143-36/+47
* radeonsi: don't use emit_data->args in build_interp_intrinsicMarek Olšák2018-08-141-19/+13
* radeonsi: inline atomic_fetch_argsMarek Olšák2018-08-141-74/+51
* radeonsi: inline store_fetch_argsMarek Olšák2018-08-141-61/+42
* radeonsi: inline load_fetch_argsMarek Olšák2018-08-141-39/+28
* radeonsi: merge txq_emit and resq_emitMarek Olšák2018-08-141-48/+45
* radeonsi: inline resq_fetch_argsMarek Olšák2018-08-141-62/+34
* radeonsi: inline txq_fetch_argsMarek Olšák2018-08-141-26/+7
* radeonsi: use get_resinfo directly in lower_gather4_integerMarek Olšák2018-08-141-13/+12
* radeonsi: inline tex_fetch_args into build_tex_intrinsicMarek Olšák2018-08-141-222/+188
* radeonsi: remove fetch_args callbacks for ALU instructionsMarek Olšák2018-08-142-103/+55
* radeonsi: move internal TGSI shaders into si_shaderlib_tgsi.cMarek Olšák2018-08-148-319/+348
* radeonsi: implement EXT_window_rectanglesMarek Olšák2018-08-147-2/+95
* freedreno/ir3: add support for a6xx 'merged' register setRob Clark2018-08-142-2/+24
* freedreno/ir3: small RA cleanupRob Clark2018-08-142-13/+8
* freedreno/ir3: stop hard-coding FS input regsRob Clark2018-08-147-183/+103
* freedreno/ir3: use r63.x for unused inputsRob Clark2018-08-141-3/+3
* freedreno/ir3: create all inputs in first blockRob Clark2018-08-141-17/+17
* freedreno/ir3: rename s/frag_pos/frag_vcoord/gRob Clark2018-08-142-17/+22
* freedreno/ir3: move per-generation compiler configRob Clark2018-08-143-43/+52
* freedreno: move free() into fdN_context_destroy()Rob Clark2018-08-145-2/+7
* freedreno: a2xx: ir2 updateJonathan Marek2018-08-145-545/+615
* virgl: ARB_texture_barrier supportDave Airlie2018-08-146-3/+24
* meson: Build with Python 3Mathieu Bridon2018-08-106-12/+12
* vc4: Implement texture_subdata() to directly upload tiled data.Eric Anholt2018-08-081-1/+39
* vc4: Handle partial loads/stores of tiled textures.Eric Anholt2018-08-083-60/+155
* vc4: Compile the LT image helper per cpp we might load/store.Eric Anholt2018-08-081-2/+31
* vc4: Refactor to reuse the LT tile walking code.Eric Anholt2018-08-081-24/+34
* svga: use pipe_sampler_view::target in svga_set_sampler_views()Brian Paul2018-08-081-1/+1
* svga: use SVGA3D_RS_FILLMODE for vgpu9Brian Paul2018-08-083-26/+37
* svga: add TGSI_SEMANTIC_FACE switch case in svga_swtnl_update_vdecl()Brian Paul2018-08-081-0/+1
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