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* radeonsi/gfx9: use CE RAM optimallyMarek Olšák2017-05-182-36/+134
| | | | | | | | | | | | | | On GFX9 with only 4K CE RAM, define the range of slots that will be allocated in CE RAM. All other slots will be uploaded directly. This will switch dynamically according to which slots are used by current shaders. GFX9 CE usage should now be similar to VI instead of being often disabled. Tested on VI by taking the GFX9 CE allocation codepath and setting num_ce_slots = 2 everywhere to get frequent switches between both modes. CE is still disabled on GFX9. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove CE offset alignment restrictionMarek Olšák2017-05-181-2/+1
| | | | | | | This was only needed by LOAD_CONST_RAM, which is now only used to load whole CE. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: only upload (dump to L2) those descriptors that are used by shadersMarek Olšák2017-05-184-24/+117
| | | | | | | This decreases the size of CE RAM dumps to L2, or the size of descriptor uploads without CE. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: record which descriptor slots are used by shadersMarek Olšák2017-05-185-0/+41
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: update si_ce_needed_cs_spaceMarek Olšák2017-05-181-8/+8
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: do only 1 big CE dump at end of IBs and one reload in the preambleMarek Olšák2017-05-185-37/+37
| | | | | | | | A later commit will only upload descriptors used by shaders, so we won't do full dumps anymore, so the only way to have a complete mirror of CE RAM in memory is to do a separate dump after the last draw call. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove early return in si_upload_descriptorsMarek Olšák2017-05-181-3/+0
| | | | | | | | All updates of descriptors_dirty also set dirty_mask, so the return is unnecessary. The next commit will want this function to be executed even if dirty_mask == 0. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clamp indirect index to the number of declared shader resourcesMarek Olšák2017-05-184-4/+15
| | | | | | | We'll do partial uploads of descriptor arrays, so we need to clamp against what shaders declare. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: merge sampler and image descriptor lists into oneMarek Olšák2017-05-186-112/+99
| | | | | | | | | | | | Sampler slots: slot[8], .. slot[39] (ascending) Image slots: slot[7], .. slot[0] (descending) Each image occupies 1/2 of each slot, so there are 16 images in total, therefore the layout is: slot[15], .. slot[0]. (in 1/2 slot increments) Updating image slot 2n+i (i <= 1) also dirties and re-uploads slot 2n+!i. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: merge constant and shader buffers descriptor lists into oneMarek Olšák2017-05-188-132/+152
| | | | | | | | | | Constant buffers: slot[16], .. slot[31] (ascending) Shader buffers: slot[15], .. slot[0] (descending) The idea is that if we have 4 constant buffers and 2 shader buffers, we only have to upload 6 slots. That optimization is left for a later commit. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: get the sampler view type from inst->Texture for TG4Samuel Pitoiset2017-05-181-7/+3
| | | | | | | | | This will also magically fix this special lowering for bindless samplers. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: add radeon_info::num_{sdma,compute}_ringsNicolai Hähnle2017-05-181-2/+2
| | | | | | Vulkan needs them. Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: move struct radeon_info to ac_gpu_info.hNicolai Hähnle2017-05-181-61/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: move surface definitions to new header ac_surface.hNicolai Hähnle2017-05-181-147/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* vc4: Don't allocate new BOs to avoid synchronization when they're shared.Eric Anholt2017-05-171-1/+2
| | | | | | | If X11 did a software fallback to the entire screen, we would throw out the BO the screen is scanning out from and allocate a new one. Cc: [email protected]
* vc4: Drop pointless indirections around BO import/export.Eric Anholt2017-05-173-69/+49
| | | | | | I've since found them to be more confusing by adding indirections than clarifying by screening off resources from the handle/fd import/export process.
* vc4: Drop the u_resource_vtbl no-op layer.Eric Anholt2017-05-174-33/+27
| | | | | We only ever attached one vtbl, so it was a waste of space and indirections.
* gallium/radeon: use a top-of-pipe timestamp for the start of TIME_ELAPSEDMarek Olšák2017-05-171-2/+19
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTIONMarek Olšák2017-05-1715-0/+15
| | | | | | for skipping mapped-buffer checking in every GL draw call Reviewed-by: Nicolai Hähnle <[email protected]>
* swr: don't use AttributeSet with llvm >= 5Tim Rowley2017-05-171-15/+21
| | | | | | | | | | | This change fixes the build break with llvm-svn. r301981 of llvm-svn made add/remove of function attributes use AttrBuilder instead of AttributeList. Tested with llvm-3.9, llvm-4.0, llvm-svn. Reviewed-by: Bruce Cherniak <[email protected]>
* freedreno/gmem: fix hw binning hangs with large render targetsRob Clark2017-05-163-3/+13
| | | | | | | | On all 3 gens, we have 4 bits for width and height in the VSC pipe config. And overflow results in setting width and/or height to zero which causes hangs. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix crash with atomicsRob Clark2017-05-161-2/+9
| | | | | | Atomics can have a result value. And sometimes it is even used. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: remove unneeded assertRob Clark2017-05-161-3/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: fallback to slow-clear for z32Rob Clark2017-05-164-11/+36
| | | | | | | We probably *could* do this with blit path, but I think it would involve clobbering settings from batch->gmem (see emit_zs()). Signed-off-by: Rob Clark <[email protected]>
* etnaviv: increment the resource seqno in resource_changedPhilipp Zabel2017-05-161-5/+1
| | | | | | | | | | Just increment the resource seqno instead of setting the texture seqno to be lower by one than the resource seqno. Signed-off-by: Philipp Zabel <[email protected]> Signed-off-by: Lucas Stach <[email protected]> Reviewed-By: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: clean up sampler view reference countingLucas Stach2017-05-161-3/+3
| | | | | | | | Use the proper pipe_resource_reference function instead of rolling our own. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: apply feature overrides in one central locationLucas Stach2017-05-165-10/+19
| | | | | | | | | This way we can just test the feature bits and don't need to spread the debug overrides to all locations touching a feature. Signed-off-by: Lucas Stach <[email protected]> Reviewed-By: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: allow R/B swapped surfaces to be clearedLucas Stach2017-05-161-0/+2
| | | | | | | Fixes: 7f62ffb68ad ("etnaviv: add support for rb swap") Cc: [email protected] Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: stop oversizing buffer resourcesLucas Stach2017-05-161-1/+1
| | | | | | | | | | | | | | PIPE_BUFFER is a target enum, not a binding. This caused the driver to up-align the height of buffer resources, leading to largely oversizing those resources. This is especially bad, as the buffer resources used by the upload manager are already 1MB in size. Height alignment meant that those would result in 4 to 8MB big BOs. Fixes: c9e8b49b885 ("etnaviv: gallium driver for Vivante GPUs") Cc: [email protected] Signed-off-by: Lucas Stach <[email protected]> Reviewed-By: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* radeonsi: extract TGSI memory/texture opcode handling into its own fileNicolai Hähnle2017-05-165-1841/+1886
| | | | | | It's about time to get the growth of si_shader.c somewhat under control. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: make const_array externally accessibleNicolai Hähnle2017-05-162-13/+15
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: make get_bounded_indirect_index externally accessibleNicolai Hähnle2017-05-162-16/+20
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: make emit_waitcnt externally accessibleNicolai Hähnle2017-05-162-10/+12
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: silence a Coverity warningNicolai Hähnle2017-05-161-0/+2
| | | | | | | | | | | | Coverity doesn't understand that we'll never pass non-NULL for vertex shaders. This is a bit lame, actually. A straightforward cross-procedural analysis limited to this source file should be enough to prove that there's no NULL-pointer dereference. Oh well. CID: 1405999 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: rename tcs_tes_uses_prim_id for clarityNicolai Hähnle2017-05-163-9/+9
| | | | | | | | What we care about is whether PrimID is used while tessellation is enabled; whether it's used in TCS/TES or further down the pipeline is irrelevant. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix gl_PrimitiveIDIn in geometry shader when using tessellationNicolai Hähnle2017-05-161-0/+2
| | | | | | | | | | | This builds on commit 0549ea15ec38 ("radeonsi: fix primitive ID in fragment shader when using tessellation"). Fixes piglit arb_tessellation_shader/execution/gs-primitiveid-instanced.shader_test Cc: 17.1 <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: enable threaded_contextMarek Olšák2017-05-151-3/+34
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/radeon: add threaded context counter monitoring for HUDMarek Olšák2017-05-153-0/+25
| | | | | | | | | "tc" will be initialized by the next commit. v2: rename stuff according to v2 changes in u_threaded_context Reviewed-by: Nicolai Hähnle <[email protected]> (v1) Tested-by: Dieter Nützel <[email protected]>
* radeonsi: implement replace_buffer_storage for the threaded contextMarek Olšák2017-05-153-13/+55
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/radeon: subclass and handle threaded_queryMarek Olšák2017-05-152-7/+12
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/radeon: subclass threaded_transferMarek Olšák2017-05-153-25/+25
| | | | | | | v2: use assert on rtransfer->b.staging Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/radeon: subclass threaded_resourceMarek Olšák2017-05-153-18/+22
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/radeon: handle other map buffer flags from the threaded contextMarek Olšák2017-05-151-2/+4
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/radeon: handle TC_TRANSFER_MAP_THREADED_UNSYNCMarek Olšák2017-05-153-1/+14
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/radeon: unwrap a context if we get a wrapped oneMarek Olšák2017-05-153-5/+9
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/radeon: require both WRITE and FLUSH_EXPLICIT in buffer_flush_regionMarek Olšák2017-05-151-2/+4
| | | | | | | spotted randomly. Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi/gfx9: add support for RavenMarek Olšák2017-05-153-2/+10
| | | | | | Cc: 17.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* Revert "freedreno: use bypass if only clears"Rob Clark2017-05-141-4/+1
| | | | | | | Causing issues with stk on a4xx.. still probably a good idea, but seems some debugging is needed first. This reverts commit 3ab072d3c8643c66d8e07e63df970b792728bac6.
* freedreno: fix crash when flush() but no renderingRob Clark2017-05-141-0/+6
| | | | | | | | | | If we haven't created a batch, just bail in pipe->flush(), since there is nothing to do. Fixes crash in warsow, which creates a whole bunch of contexts used for nothing but texture uploads. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix indexbuffer uploadRob Clark2017-05-146-15/+26
| | | | | | | | My fault for not having time to test Marek's patches while they were on list. Fixes: 330d0607 ("gallium: remove pipe_index_buffer and set_index_buffer") Signed-off-by: Rob Clark <[email protected]>
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