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* freedreno/ir3: convert dynamic arrays to rallocRob Clark2017-04-143-14/+8
| | | | | | | Want to move one of these under ir3_block, so that gives a reason to migrate the remaining malloc/realloc to ralloc. Signed-off-by: Rob Clark <[email protected]>
* swr: add linux to scons buildGeorge Kyriazis2017-04-141-6/+1
| | | | | | Make swr compile for both linux and windows. Reviewed-by: Tim Rowley <[email protected]>
* gallium/radeon: never use staging buffers with AMD_pinned_memoryNicolai Hähnle2017-04-131-2/+16
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* radeonsi: fix gl_BaseVertex in non-indexed drawsNicolai Hähnle2017-04-133-4/+23
| | | | | | | | | | | | | | | | | | | gl_BaseVertex is supposed to be 0 in non-indexed draws. Unfortunately, the way they're implemented, the VGT always generates indices starting at 0, and the VS prolog adds the start index. There's a VGT_INDX_OFFSET register which causes the VGT to start at a driver-defined index. However, this register cannot be written from indirect draws. So fix this unlikely case by setting a bit to tell the VS whether the draw is indexed or not, so that gl_BaseVertex can be adjusted accordingly when used. Fixes a bug in KHR-GL45.shader_draw_parameters_tests.ShaderMultiDrawArraysParameters.* Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: provide VS_STATE input to all VS variantsNicolai Hähnle2017-04-135-27/+18
| | | | | | v2: fix incorrect change in get_tcs_out_patch_stride Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: change the bit-packing of LS out/TCS in dataNicolai Hähnle2017-04-133-9/+14
| | | | | | Avoid conflicts when merging various VS state bits. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: emit VS_STATE register explicitly from si_draw_vboNicolai Hähnle2017-04-136-2/+27
| | | | | | We will merge other derived state information into this register. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: extract derived tess state emit to higher levelNicolai Hähnle2017-04-131-6/+7
| | | | | | | Especially with subsequent changes, this makes it easier to see the sequence of state emits at the higher level. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: drop support for TGSI_SEMANTIC_VERTEXID_NOBASENicolai Hähnle2017-04-131-2/+3
| | | | | | It is unused. Reviewed-by: Marek Olšák <[email protected]>
* llvmpipe: remove unused subpixel_snap() and fixed_to_float()Samuel Pitoiset2017-04-131-6/+3
| | | | | | | | | | | | | | | | Fixes the following Clang warnings. lp_setup_tri.c:55:1: warning: unused function 'subpixel_snap' [-Wunused-function] subpixel_snap(float a) ^ lp_setup_tri.c:61:1: warning: unused function 'fixed_to_float' [-Wunused-function] fixed_to_float(int a) ^ v2: - do not remove subpixel_snap() (use !PIPE_ARCH_SSE instead) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* softpipe: remove unused sp_exec_fragment_shader()Samuel Pitoiset2017-04-131-8/+0
| | | | | | | | | | | | Fixes the following Clang warning. sp_fs_exec.c:56:1: warning: unused function 'sp_exec_fragment_shader' [-Wunused-function] sp_exec_fragment_shader(const struct sp_fragment_shader_variant *var) ^ 1 warning generated. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* softpipe: remove unused quad_shade_stage()Samuel Pitoiset2017-04-131-8/+0
| | | | | | | | | | | | Fixes the following Clang warning. sp_quad_fs.c:60:1: warning: unused function 'quad_shade_stage' [-Wunused-function] quad_shade_stage(struct quad_stage *qs) ^ 1 warning generated. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* softpipe: remove unused get_texel_quad_2d()Samuel Pitoiset2017-04-131-17/+0
| | | | | | | | | | | | | Fixes the following Clang warning. sp_tex_sample.c:802:1: warning: unused function 'get_texel_quad_2d' [-Wunused-function] get_texel_quad_2d(const struct sp_sampler_view *sp_sview, ^ CC sp_tile_cache.lo 1 warning generated. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* trace: remove some unused trace_dump_tag*() functionsSamuel Pitoiset2017-04-131-52/+0
| | | | | | | | | | | | | | | | | | | Fixes the following Clang warnings. tr_dump.c:137:1: warning: unused function 'trace_dump_tag' [-Wunused-function] trace_dump_tag(const char *name) ^ tr_dump.c:168:1: warning: unused function 'trace_dump_tag_begin2' [-Wunused-function] trace_dump_tag_begin2(const char *name, ^ tr_dump.c:187:1: warning: unused function 'trace_dump_tag_begin3' [-Wunused-function] trace_dump_tag_begin3(const char *name, ^ CC tr_texture.lo 3 warnings generated. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* virgl: add missing PIPE_CAP_DOUBLESSamuel Pitoiset2017-04-131-0/+1
| | | | | | | | | | | | Fixes the following Clang warning. virgl_screen.c:60:12: warning: enumeration value 'PIPE_CAP_DOUBLES' not handled in switch [-Wswitch] switch (param) { ^ 1 warning generated. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nvc0: Enable ARB_shader_ballot on Kepler+Boyan Ding2017-04-131-1/+2
| | | | | | | | readInvocationARB() and readFirstInvocationARB() need SHFL.IDX instruction which is introduced in Kepler. Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0/ir: Implement TGSI_OPCODE_BALLOT and TGSI_OPCODE_READ_*Boyan Ding2017-04-131-0/+31
| | | | | | | v2: Check if each channel is masked in TGSI_OPCODE_BALLOT (Ilia Mirkin) Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0/ir: Implement TGSI_SEMANTIC_SUBGROUP_*Boyan Ding2017-04-131-0/+27
| | | | | Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0/ir: Add SV_LANEMASK_* system values.Boyan Ding2017-04-135-0/+25
| | | | | | | v2: Add name strings in nv50_ir_print.cpp (Ilia Mirkin) Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0/ir: Allow 0/1 immediate value as source of OP_VOTEBoyan Ding2017-04-133-11/+60
| | | | | | | | | | | | | | | | | | | | Implementation of readFirstInvocationARB() on nvidia hardware needs a ballotARB(true) used to decide the first active thread. This expressed in gm107 asm as (supposing output is $r0): vote any $r0 0x1 0x1 To model the always true input, which corresponds to the second 0x1 above, we make OP_VOTE accept immediate value 0/1 and emit "0x1" and "not 0x1" in the src field respectively. v2: Make sure that asImm() is not NULL (Samuel Pitoiset) v3: (Ilia Mirkin) Make the handling more symmetric with predicate version in gm107 Use i->getSrc(s) Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gk110/ir: Emit OP_SHFLBoyan Ding2017-04-131-0/+56
| | | | | | | | | v2: Make sure that asImm() is not NULL (Samuel Pitoiset) v3: Check the range of immediate in OP_SHFL (Ilia Mirkin) Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0/ir: Emit OP_SHFLBoyan Ding2017-04-131-0/+53
| | | | | | | | | | | | | v2: (Samuel Pitoiset) Add an assertion to check if the target is Kepler Make sure that asImm() is not NULL v3: (Ilia Mirkin) Check the range of immediate value of OP_SHFL Use the new setPDSTL API Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0/ir: Properly handle a "split form" of predicate destinationBoyan Ding2017-04-131-2/+13
| | | | | | | | | | | | | | GF100's ISA encoding has a weird form of predicate destination where its 3 bits are split across whole the instruction. Use a dedicated setPDSTL function instead of original defId which is incorrect in this case. v2: (Ilia Mirkin) Change API of setPDSTL() to handle cases of no output Fix setting of the highest bit in setPDSTL() Cc: [email protected] Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gm107/ir: Emit third src 'bound' and optional predicate output of SHFLBoyan Ding2017-04-132-9/+29
| | | | | | | | v2: Emit the original hard-coded 0x1c03 when OP_SHFL is used in gm107's lowering (Samuel Pitoiset) Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* Revert "r600g: get rid of dummy pixel shader"Marek Olšák2017-04-123-30/+40
| | | | | | | | This reverts commit 61e47d92c5196bf0240e322bb1b9d305836559e3. It causes a hang on RS780. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100663
* swr: [rasterizer core] Disable 8x2 tile backendTim Rowley2017-04-111-1/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer common] Add _simd_testz_si aliasTim Rowley2017-04-111-0/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer archrast] Fix archrast for MSVC 2017 compilerTim Rowley2017-04-115-6/+6
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer jitter] Remove unused functionTim Rowley2017-04-112-35/+0
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer jitter] Remove HAVE_LLVM tests supporting llvm < 3.8Tim Rowley2017-04-114-52/+0
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer common/core] Fix 32-bit windows buildTim Rowley2017-04-116-117/+123
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] Fix unused variable warningsTim Rowley2017-04-113-10/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] Code formating changeTim Rowley2017-04-111-10/+10
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] SIMD16 Frontend WIP - PATim Rowley2017-04-111-22/+22
| | | | | | Fix PA NextPrim for SIMD8 on SIMD16. Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] SIMD16 Frontend WIP - ClipperTim Rowley2017-04-115-124/+941
| | | | | | Implement widened clipper for SIMD16. Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] Multisample sample position setup changeTim Rowley2017-04-113-75/+92
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] Reduce templates to speed compileTim Rowley2017-04-113-10/+71
| | | | | | | Quick patch to remove some unused template params to cut down rasterizer compile time. Reviewed-by: Bruce Cherniak <[email protected]>
* swr: return true for PIPE_CAP_DOUBLESTim Rowley2017-04-111-0/+1
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* etnaviv: enable TS, but disable autodisableLucas Stach2017-04-111-2/+2
| | | | | | | | Autodisable seems to cause missed rendering in some cases, but otherwise TS seems to work properly. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]>
* etnaviv: enable TS also on sampler resourcesLucas Stach2017-04-111-3/+0
| | | | | | | | | | | Fixes a performance issue with imported winsys buffers as those are marked with binding sampler view. This might require a TS flush on single pipe chips that directly sample from the rendered buffer, but otherwise seems to work fine. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]>
* etnaviv: align TS surface size to number of pixel pipesLucas Stach2017-04-111-1/+2
| | | | | | | | | | The TS surface gets cleared by a tiled RS fill. If the chip has more than 1 pixel pipe the size of the TS surface needs to be aligned so that each pipe address matches a tile start, otherwise the RS will hang. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]>
* etnaviv: avoid using invalid TSLucas Stach2017-04-113-1/+7
| | | | | | | | | | | The TS is only valid after it has been initialized by a fast clear, so it should not be taken into account when blitting resources that haven't been cleared. Also the blit itself invalidates the destination TS, as it's not updated and will retain data from the previous rendering after the blit. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]>
* nouveau: when mapping a persistent buffer, synchronize on former xfersIlia Mirkin2017-04-111-4/+2
| | | | | | | | | If the buffer is being used, we should wait for those uses to be complete before returning the map. Fixes: GL45-CTS.direct_state_access.buffers_functional Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nvc0: increase texture buffer object alignment to 256 for pre-GM107Ilia Mirkin2017-04-111-1/+1
| | | | | | | | | | | | | We currently don't pass the low byte of the address via the surface info, so in order to work with images, these have to implicitly be aligned to 256. The proprietary driver also doesn't go out of its way to provide lower alignment. Fixes GL45-CTS.texture_buffer.texture_buffer_texture_buffer_range Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected] Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/radeon: add HUD queries for GPU temperature and clocksSamuel Pitoiset2017-04-101-6/+6
| | | | | | | | | | | | | | | Only the Radeon kernel driver exposed the GPU temperature and the shader/memory clocks, this implements the same functionality for the AMDGPU kernel driver. These queries will return 0 if the DRM version is less than 3.10, I don't explicitely check the version here because the query codepath is already a bit messy. v2: - rebase on top of master Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add new si_check_render_feedback_texture() helperSamuel Pitoiset2017-04-101-45/+44
| | | | | | | For bindless. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add new si_decompress_color_texture() helperSamuel Pitoiset2017-04-101-13/+17
| | | | | | | For bindless. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add new depth_needs_decompression() helperSamuel Pitoiset2017-04-101-2/+8
| | | | | | | v2: - rename to depth_needs_decompression() instead Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add a 'break' in si_check_render_feedback_*()Samuel Pitoiset2017-04-101-2/+6
| | | | | | | No need to check all color buffers. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: re-use 'desc' in si_set_shader_image()Samuel Pitoiset2017-04-101-2/+1
| | | | | | | No need to compute the offset in the descriptor twice. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
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