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* freedreno/a4xx: rework vinterp/vpsreplRob Clark2015-11-261-12/+36
| | | | | | Same as previous commit, for a4xx. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: rework vinterp/vpsreplRob Clark2015-11-261-12/+37
| | | | | | | | | | | | Make the interpolation / point-sprite replacement mode setup deal with varying packing. In a later commit, we switch to packing just the varying components that are actually used by the frag shader, so we won't be able to assume everything is vec4's aligned to vec4. Which would highly confuse the previous vinterp/vpsrepl logic. Signed-off-by: Rob Clark <[email protected]>
* radeon: use PIPE_DRIVER_QUERY_FLAG_DONT_LIST for perfcountersNicolai Hähnle2015-11-261-0/+2
| | | | | | | | Since the query names are not very enlightening, and there are thousands of them, GALLIUM_HUD=help should only show the first and last query name for each hardware block. Reviewed-by: Marek Olšák <[email protected]>
* radeon: delay the generation of driver query names until first useNicolai Hähnle2015-11-263-104/+113
| | | | | | | This shaves a bit more time off the startup of programs that don't actually use performance counters. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/compute: Use the compiler's COMPUTE_PGM_RSRC* register valuesTom Stellard2015-11-252-31/+7
| | | | | | | | | The compiler has more information and is able to optimize the bits it sets in these registers. Reviewed-by: Marek Olšák <[email protected]> CC: <[email protected]>
* radeonsi: Rename si_shader::ls_rsrc{1,2} to si_shader::rsrc{1,2}Tom Stellard2015-11-253-6/+6
| | | | | | In the future, these will be used by other shaders types. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: implement AMD_performance_monitor for CIK+Nicolai Hähnle2015-11-2510-3/+1486
| | | | | | | | | | | | | | | | | | Expose most of the performance counter groups that are exposed by Catalyst. Ideally, the driver will work with GPUPerfStudio at some point, but we are not quite there yet. In any case, this is the reason for grouping multiple instances of hardware blocks in the way it is implemented. The counters can also be shown using the Gallium HUD. If one is interested to see how work is distributed across multiple shader engines, one can set the environment variable RADEON_PC_SEPARATE_SE=1 to obtain finer-grained performance counter groups. Part of the implementation is in radeon because an implementation for older hardware would largely follow along the same lines, but exposing a different set of blocks which are programmed slightly differently. Reviewed-by: Marek Olšák <[email protected]>
* radeon: scale query buffer size to result sizeNicolai Hähnle2015-11-251-1/+1
| | | | | | | Performance monitor queries can become very big, especially considering that instances of a block in different shader engines are queried separately. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/sid: add performance counter registersNicolai Hähnle2015-11-251-0/+1013
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/sid: add hardware constants for COPY_DATA packetNicolai Hähnle2015-11-251-0/+3
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeon: extend CIK_UCONFIG_REG_END for performance countersNicolai Hähnle2015-11-252-2/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeon: add perfcounter-related EVENT_TYPEsNicolai Hähnle2015-11-251-0/+3
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeon: additional constants for WAIT_REG_MEM and EVENT_WRITE_EOPNicolai Hähnle2015-11-251-0/+8
| | | | Reviewed-by: Marek Olšák <[email protected]>
* nouveau: move interlaced assert down in nouveau_vp3_video_buffer_createJulien Isorce2015-11-251-1/+1
| | | | | | | | templat->interlaced is 0 if not NV12 which is the case currently when using VPP. Signed-off-by: Julien Isorce <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* softpipe/llvmpipe: don't advertize support for ASTCRoland Scheidegger2015-11-242-2/+4
| | | | | | | | | 33339775565154040e0c4ea2e196217dccc08cdf added support for ASTC textures to gallium. They don't have any helpers hooked up for software decoding, however, so cannot support them in drivers relying on util code for decoding. Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* llvmpipe: don't test for unsupported formats in lp_test_formatRoland Scheidegger2015-11-241-0/+12
| | | | | | | | | | | | | Removing the fake format helpers (1c7d0a6aa4f5cb38af7e281e1e5437cd1a20f781) caused this to fail. These formats were never supported, but previously they would have asserted in the generated jit functions (which, due to lack of test cases for these formats, were never called) whereas we now assert when trying to build the jit function. So, skip them completely. This fixes https://bugs.freedesktop.org/show_bug.cgi?id=93092 Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* radeon/llvm: Use llvm.AMDIL.exp intrinsic again for nowMichel Dänzer2015-11-241-1/+1
| | | | | | | | llvm.exp2.f32 doesn't work in some cases yet. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92709 Reviewed-by: Nicolai Hähnle <[email protected]>
* radeon/uvd: uv pitch separation for stoneyBoyuan Zhang2015-11-232-1/+6
| | | | | | | | v2: set the behaviour default for future ASICs. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Cc: [email protected]
* svga: Add ASTC formats to format table.Jose Fonseca2015-11-231-0/+28
| | | | | | Fixes build. Otherwise untested. Trivial.
* freedreno/ir3: add support for a few gs5 opsIlia Mirkin2015-11-231-0/+27
| | | | | | | Tested on a4xx. This is part of the builtins added by ARB_gpu_shader5 and GLSL ES 3.10. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a4xx: add ARB_texture_query_lod supportIlia Mirkin2015-11-232-6/+20
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a4xx: re-emit program on dirty framebufferIlia Mirkin2015-11-231-1/+1
| | | | | | | The program emit depends on certain fb details. Make sure those get updated when the fb changes. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a4xx: use a factor of 32767 for snorm8 blendingIlia Mirkin2015-11-231-5/+34
| | | | | | | | | | | | It appears that the hardware wants the integer to be scaled the same way that the hardware representation is. snorm16 uses one of the float factors, so this is only relevant for snorm8. This fixes a number of subcases of bin/fbo-blending-formats GL_EXT_texture_snorm Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* freedreno/a4xx: only compute texture offset once for the viewIlia Mirkin2015-11-233-13/+6
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a4xx: add ARB_texture_view supportIlia Mirkin2015-11-233-8/+10
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a4xx: add formats for ARB_texture_buffer_object_rgb32 supportIlia Mirkin2015-11-233-3/+9
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a4xx: add ARB_texture_rgb10_a2ui supportIlia Mirkin2015-11-232-2/+3
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a4xx: add astc formatsIlia Mirkin2015-11-232-1/+39
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a4xx: support 16384 texels in buffer textureIlia Mirkin2015-11-232-5/+4
| | | | | | Looks like the width field's bitmask was off-by-one. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a4xx: add ARB_texture_buffer_range supportIlia Mirkin2015-11-233-15/+41
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a4xx: add polygon mode supportIlia Mirkin2015-11-234-4/+26
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nir: s/nir_type_unsigned/nir_type_uintJason Ekstrand2015-11-231-1/+1
| | | | | | | | | | | v2: do the same in tgsi_to_nir (Samuel) v3: added missing cases after rebase (Iago) v4: Add a blank space after '#' in one of the comments (Matt) Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nv50/ir: fix (un)spilling of 3-wide resultsIlia Mirkin2015-11-221-4/+42
| | | | | | | | | There is no 96-bit load/store operations, so we have to split it up into a 32-bit parts, with a split/merge around it. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90348 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nv50,nvc0: properly handle buffer storage invalidation on dsa bufferIlia Mirkin2015-11-222-15/+17
| | | | | | | | | In case that the buffer has no bind at all, assume it can be a regular buffer. This can happen on buffers created through the ARB_dsa interfaces. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nouveau: use the buffer usage to determine placement when no bindingIlia Mirkin2015-11-221-2/+6
| | | | | | | | | | | With ARB_direct_state_access, buffers can be created without any binding hints at all. We still need to allocate these buffers to VRAM or GART, as we don't have logic down the line to place them into GPU-mappable space. Ideally we'd be able to shift these things around based on usage. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92438 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* vc4: Just put USE_VC4_SIMULATOR in DEFINES.Eric Anholt2015-11-222-5/+0
| | | | | | | | In the pipe-loader reworks, it was missed in one of the new directories it was used. Cc: [email protected] Reviewed-by: Emil Velikov <[email protected]>
* vc4: Use nir_channel() to simplify all of our nir_swizzle() cases.Eric Anholt2015-11-212-6/+5
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* vc4: Fix point size lookup.Eric Anholt2015-11-211-1/+1
| | | | | | | | I think I may have regressed this in the NIR conversion. TGSI-to-NIR is putting the PSIZ in the .x channel, not .w, so we were grabbing some garbage for point size, which ended up meaning just not drawing points. Fixes glean pointAtten and pointsprite.
* freedreno/a4xx: disable blending and alphatest for integer rt0Ilia Mirkin2015-11-211-2/+13
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* freedreno/a4xx: fix independent blendIlia Mirkin2015-11-212-2/+3
| | | | | | | This fixes the ext_draw_buffers2 and arb_draw_buffers_blend tests. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* freedreno/a4xx: enable ARB_base_instance supportIlia Mirkin2015-11-211-1/+1
| | | | | | We already pass in start_instance in fd4_draw. Expose the extension. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a4xx: set fetchsize in mem2gmem texture restoreIlia Mirkin2015-11-211-1/+2
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a4xx: add 11_11_10_float vertex type supportIlia Mirkin2015-11-212-1/+2
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a4xx: fix 3d texture setupIlia Mirkin2015-11-213-3/+7
| | | | | | | | | | Same fix as on a3xx - set the second (tiny) layer size bitfield to the smallest level's size so that the hw knows not to minify beyond that. This fixes texelFetch sampler3D piglits. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* freedreno/a4xx: only align slices in non-layer_first texturesIlia Mirkin2015-11-211-2/+4
| | | | | | | | | | | | When layer is the container, slices are tightly packed inside of each layer. We don't need any additional alignment. On a3xx, each slice contains all the layers, so having alignment makes sense. This fixes a whole slew of array-related piglits, including texelFetch and tex-miplevel-selection varieties. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* {st,targets}/dri: use static/dynamic pipe-loaderEmil Velikov2015-11-211-3/+0
| | | | | | | | | | Covert DRI to use only the pipe-loader interface. With drisw_create_screen and kms_swrast_create_screen replaced by their pipe-loader equivalent, we can now drop them. Signed-off-by: Emil Velikov <[email protected]> Acked-by: Rob Clark <[email protected]>
* configure: use HAVE_DRISW_KMS when handling kms swrastEmil Velikov2015-11-211-1/+1
| | | | | | | Using HAVE_DRI2 to manage it seems counter-intuitive. Signed-off-by: Emil Velikov <[email protected]> Acked-by: Rob Clark <[email protected]>
* gallium/trace: remove useless NULL check from trace_screen_create()Emil Velikov2015-11-211-3/+0
| | | | | | | | | Currently every target makes sure that the screen is non-null prior to using the debug (trace including) wrappers. If that no longer holds true we want to know and fix this ASAP rather than silently bailing out. Signed-off-by: Emil Velikov <[email protected]> Acked-by: Rob Clark <[email protected]>
* freedreno/a4xx: add missing formats to enable ARB_vertex_type_2_10_10_10_revIlia Mirkin2015-11-202-4/+8
| | | | | | | Same as commit 84d087aea but for a4xx. The RE'd enums had the same issue too. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a4xx: use hardware RGTC texture samplersIlia Mirkin2015-11-206-24/+19
| | | | | | | | | a4xx hardware has real support for RGTC so there's no need to fake it like we do on a3xx. Undo the hacks, and keep track of an "internal format" of a resource, which on a3xx will be different, triggering the transfer-time conversions to take place. Signed-off-by: Ilia Mirkin <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 13:33:33 +0000