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* iris: Don't bother with PIPE_CONTROLs for CPU writes and no historyKenneth Graunke2019-06-201-6/+9
| | | | | | | | | | | | | If a buffer has no usage history, we don't have any read only cache invalidates to do. If we've written it with the CPU, we don't need to flush the render cache. The only bit remaining is the CS stall from iris_flush_bits_for_history. We can just skip the PIPE_CONTROL in this case. This is pretty common - an app creates a buffer, fills it with data, and then binds it for some purpose. Cuts 36% of the flushes in Manhattan 3.0 on Kabylake GT2.
* iris: Only do an RT flush for transfer maps if using copy_region.Kenneth Graunke2019-06-201-1/+1
| | | | | | If we wrote the data via the CPU, there's no point in doing a render target flush. If using BLORP, we do want a render target flush so the data lands.
* iris: Use iris_flush_bits_for_history in iris_transfer_flush_regionKenneth Graunke2019-06-201-5/+12
| | | | | | | Instead of using the combined iris_flush_and_dirty_for_history, use iris_flush_bits_for_history directly - we were already using the split out iris_dirty_for_history. There's no need to dirty twice, and we can avoid the looping altogether for non-buffers.
* iris: Avoid double flushing in iris_transfer_flush_region when copying.Kenneth Graunke2019-06-201-4/+3
| | | | | | | | | | My intention was to have iris_copy_region not do flushing, and leave that up to the callers. iris_resource_copy_region needs to do this, but iris_transfer_flush_region was already doing it. The net result was that we were doing it twice for transfers. So, move the flushing from iris_copy_region to iris_resource_copy_region so that it only happens in the callers as I intended.
* iris: Fix iris_flush_and_dirty_history to actually dirty history.Kenneth Graunke2019-06-201-0/+2
| | | | | | | When I split iris_flush_and_dirty_history into two helper functions, I accidentally made it stop dirtying. Which was...sort of the point. Fixes: 21688a306b2 iris: Split iris_flush_and_dirty_for_history into two helpers.
* iris: Add maybe_flush calls to texture_barrier and memory_barrierKenneth Graunke2019-06-201-0/+3
| | | | | | | | | Otherwise, tests which loop on glMemoryBarrier may run us out of batch space with piles of flushing. (Ideally, we'd elide those bonus PIPE_CONTROLs, but presumably this isn't that common of a case...) Piglit's arb_pipeline_statistics_query-comp would hit this case after some of the next patches remove other PIPE_CONTROLs with maybe_flushes.
* iris: Implement INTEL_DEBUG=pc for pipe control logging.Kenneth Graunke2019-06-2011-57/+168
| | | | | | | | This prints a log of every PIPE_CONTROL flush we emit, noting which bits were set, and also the reason for the flush. That way we can see which are caused by hardware workarounds, render-to-texture, buffer updates, and so on. It should make it easier to determine whether we're doing too many flushes and why.
* panfrost: Skip shading unaffected tilesAlyssa Rosenzweig2019-06-205-2/+51
| | | | | | | | | | | Looking at the scissor, we can discard some tiles. We specifially don't care about the scissor on the wallpaper, since that's a no-op if the entire tile is culled. v2: Clarify clear comment (not reviewed but trivial). Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* panfrost: Set job requirements during drawTomeu Vizoso2019-06-202-1/+2
| | | | | | | | | | | Right now we are doing it at a moment when we don't have all the information we need. Signed-off-by: Tomeu Vizoso <[email protected]> Suggested-by: Alyssa Rosenzweig <[email protected]> Acked-by: Rohan Garg <[email protected]> Cc: Rohan Garg <[email protected]> Fixes: bfca21b622df ("panfrost: Figure out job requirements in pan_job.c")
* panfrost/meson: Link with libpanfrost_sharedAlyssa Rosenzweig2019-06-201-1/+1
| | | | | | Fixes: 035a07c0 ("panfrost: Switch to lima tiling") Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Load from tiled imagesAlyssa Rosenzweig2019-06-201-2/+15
| | | | | | | Now that we have lima tiling code available, use it to load from a tiled source. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Switch to lima tilingAlyssa Rosenzweig2019-06-205-265/+11
| | | | | | | | | Lima and Panfrost both have implementations of software tiling (the Lima one was forked off the Panfrost one which was forked off the original Lima one...). Switch to the most recent Lima code, since it's more complete than ours at this point. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Fix tiled NPOT textures with bpp<4Alyssa Rosenzweig2019-06-201-3/+3
| | | | | | | | | Panfrost's tiling routines (incorrectly) ignored the source stride, masking this bug; lima's routines respect this stride, causing issues when tiling NPOT textures whose stride is not a multiple of 64 (for instance, NPOT textures with bpp=1). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* lima,panfrost: Move lima_tiling.c/h to /src/panfrostAlyssa Rosenzweig2019-06-206-239/+8
| | | | | | | | | | | This will allow both drivers to share this code. Both drivers build-tested with meson. Android build not tested. v2: Change naming from tiling->shared, in case Lima and Panfrost can share more in the future. Fix Android build system. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-and-tested-by: Qiang Yu <[email protected]>
* iris: Use render_batch/compute_batch locals in memory_barrierKenneth Graunke2019-06-201-4/+4
| | | | We have them, may as well use them.
* panfrost: Remove other commented pointersAlyssa Rosenzweig2019-06-201-4/+0
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/decode: Elide more zero fieldsAlyssa Rosenzweig2019-06-201-6/+16
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/decode: Remove memory commentsAlyssa Rosenzweig2019-06-201-20/+0
| | | | | | These do more harm than good at this point. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add missing 0x in invocation_countAlyssa Rosenzweig2019-06-201-1/+1
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/decode: Skip decode of fragment backend in non-fragmentAlyssa Rosenzweig2019-06-201-24/+48
| | | | | | This is all zero for anything but fragment shaders. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/decode: Clip mali_compute_fbd at 64-bytesAlyssa Rosenzweig2019-06-202-18/+0
| | | | | | | | | Looking at internal evidence (later fields including a literal other compute job inception-style, seeming memory corruption, no clear function, and the field after this being a pointer to *itself*), it looks like this is really a much smaller descriptor. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/decode: Print COMPUTE uniforms as pointersAlyssa Rosenzweig2019-06-201-1/+24
| | | | | | | In OpenGL, uniforms generally represent fp32 vec4s (at least in highp mode). In OpenCL, they represent vec2s of 64-bit pointers. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/decode: Show int uniformsAlyssa Rosenzweig2019-06-201-4/+8
| | | | | | Float is ambiguous. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/decode: Expand pointers in compute descriptorAlyssa Rosenzweig2019-06-202-7/+34
| | | | | | Just as an aid. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/decode: Identify "compute FBD"Alyssa Rosenzweig2019-06-202-0/+29
| | | | | | | | There is fundamentally not a framebuffer associated with a compute job. Allocate a new structure for it so we don't mess up graphics when decoding. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Allocate panfrost_job in panfrost_contextTomeu Vizoso2019-06-201-1/+1
| | | | | Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Release transient poolsTomeu Vizoso2019-06-201-1/+7
| | | | | Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: ci: Exclude flip-flops from resultsTomeu Vizoso2019-06-201-1/+4
| | | | | | | | | | | These tests are failing at times, blacklist for now: dEQP-GLES2.functional.fbo.render.shared_colorbuffer_clear.tex2d_rgba dEQP-GLES2.functional.fbo.render.shared_colorbuffer_clear.tex2d_rgb dEQP-GLES2.functional.shaders.matrix.mul.dynamic_highp_mat4_vec4_vertex Signed-off-by: Tomeu Vizoso <[email protected]> Acked-by: Alyssa Rosenzweig <[email protected]>
* svga: Support ARB_buffer_storageThomas Hellstrom2019-06-205-9/+33
| | | | | | | | | | | | This basically boils down to supporting persistent and coherent buffer storage. We chose to use coherent buffer storage for all persistent buffers even if it's not explicitly specified, since using glMemoryBarrier to obtain coherency would be particularly expensive in our driver stack, and require a lot of additional bookkeeping. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* svga: Map vertex- index- and constant buffers ansynchronously when readingThomas Hellstrom2019-06-202-4/+9
| | | | | | | | | | | | | | | | | With SWTNL and index translation we're mapping buffers for reading. These buffers are commonly upload_mgr buffers that might already be referenced by another submitted or unsubmitted GPU command. A synchronous map will then trigger a flush and sync, at least on Linux that doesn't distinguish between read- and write referencing. So map these buffers async. If they for some obscure reason happen to be dirty (stream-output, buffer-copy), the resource_buffer code will read-back and sync anyway. For persistent / coherent buffers a corresponding read-back and sync will happen in the kernel fault handler. Testing: Piglit quick. No regressions. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* svga: Fix index buffer uploadsThomas Hellstrom2019-06-206-172/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | In the case of SWTNL and index translation we were uploading index buffers and then reading out from them using the CPU. Furthermore, when translating indices we often cached the results with an upload_mgr buffer, causing the cached indexes to be immediately discarded on the next write to that upload_mgr buffer. Fix this by only uploading when we know the index buffer is going to be used by hardware. If translating, only cache translated indices if the original buffer was not a user buffer. In the latter case when we're not caching, use an upload_mgr buffer for the hardware indices. This means we can also remove the SWTNL hand-crafted index buffer upload mechanism in favour of the upload_mgr. Finally avoid using util_upload_index_buffer(). It wastes index buffer space by trying to make sure that the offset of the indices in the upload_mgr buffer is larger or equal to the position of the indices in the source buffer. From what I can tell, the SVGA device does not require that. Testing done: Piglit quick. No regressions. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* winsys/svga: Make it possible to specify coherent resourcesThomas Hellstrom2019-06-203-2/+8
| | | | | | | | Add a flag in the surface cache key and a winsys usage flag to specify coherent memory. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* virgl: Add debug flag to bypass driconf to enable the BGRA tweaksGert Wollny2019-06-202-0/+8
| | | | | | | | This useful for testing, also because with vtest the dri configuration is not read. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: Add a tweak to set the value for emulated queries of GL_SAMPLES_PASSEDGert Wollny2019-06-205-1/+12
| | | | | | | | | | | | | | On GLES hosts GL_SAMPLES_PASSED is emulated by GL_ANY_SAMPLES_PASSED which returns a boolen. With this tweak the value that is returned if any sample passed can be set. This may be of iterest when an application decides whether some geometry is rendered based on an amount of visibility and not just a binary desicion. virgelrenderer sets a default of 1024 on th host. v2: Remove reference from virgl and correct description (Emil) v3: Send the tweak binary encoded instead of using strings (Gurchetan) Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: Add tweak to apply a swizzle when drawing/blitting to a emulated BGRA ↵Gert Wollny2019-06-205-0/+9
| | | | | | | | | | | | texture With Qemu this final swizzle is not needed, but with vtest it is, i.e. it depends on how a program using virglrenderer uses the surface that is rendered to, hence a tweak is added. v2: Update description and fix spelling (Emil) v3: Send tweak as binary value instead of using strings (Gurchetan) Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: Add driconf tweak for emulating BGRA surfaces on GLESGert Wollny2019-06-203-0/+10
| | | | | | | | | | | These tweaks are used to fix rendering issues with Valve games and at least also "The Raven Remastered" when run on a GLES host. v2: Fix type in define and remove virgl from driconf option (Emil) v3: Encode tweak binary instead of using strings (Gurchetan) Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: Add override for BGRA format to use swizzled SRGB formatGert Wollny2019-06-204-1/+27
| | | | | | | | | | | Tie in the check whether the host supports tweaks and whether this tweak is enabled. v2: Add comment about the emulated formats not being used directly in the guest (Gurchetan) Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: Add code to accept BGRx_SRGB as RGBx_SRGBGert Wollny2019-06-202-3/+23
| | | | | | | This will be enabled in later patches by the emulation tweak. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: Add skeleton to evaluate cap and send tweaksGert Wollny2019-06-205-0/+31
| | | | | Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: factor out format host bits checkGert Wollny2019-06-201-16/+17
| | | | | | | This will make it a single location when we want to replace a format. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* gallium/virgl: Add code path for virgl to read driconfGert Wollny2019-06-202-2/+3
| | | | | | | | | | | | This works only for the drm variant of virgl and not for the vtest variant. v2: Rebase, replace the configuration query function by a pointer to the configuration data. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Emil Velikov <[email protected]> (v1) Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: Add driinfo file and tie it into the buildGert Wollny2019-06-203-2/+36
| | | | | Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* ac/rtld: check correct LDS max sizeMarek Olšák2019-06-191-0/+3
| | | | Tested-by: Dieter Nützel <[email protected]>
* radeonsi: add s_sethalt to shaders for debuggingNicolai Hähnle2019-06-192-0/+4
| | | | Tested-by: Dieter Nützel <[email protected]>
* iris: Bail on queries for INTEL_NO_HW=1.Kenneth Graunke2019-06-191-0/+5
| | | | | | We don't execute any of the commands to record snapshots, so we can't actually produce a real result. We do however need to avoid waiting on a syncpt which will never be signalled. So, just return 0.
* virgl: Support VIRGL_BIND_SHAREDDavid Riley2019-06-192-0/+3
| | | | | | | Support a new virgl bind type for shared buffers. Signed-off-by: David Riley <[email protected]> Reviewed-By: Gert Wollny <[email protected]>
* ac,radeonsi: Always mark buffer stores as inaccessiblememonlyConnor Abbott2019-06-193-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | inaccessiblememonly means that it doesn't modify memory accesible via normal LLVM pointers. This lets LLVM's dead store elimination, memcpy forwarding, etc. ignore functions with this attribute. We don't represent descriptors as pointers, so this property is always true of buffer and image stores. There are plans to represent descriptors via pointers, but this just means that now nothing is inaccessiblememonly, as LLVM will then understand loads/stores via its usual alias analysis. Radeonsi was mistakenly only setting it if the driver could prove that there were no reads, and then it was cargo-culted into ac_llvm_build and ac_llvm_to_nir. Rip it out of everything. statistics with nir enabled: Totals from affected shaders: SGPRS: 152 -> 152 (0.00 %) VGPRS: 128 -> 132 (3.12 %) Spilled SGPRs: 0 -> 0 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 9324 -> 9244 (-0.86 %) bytes LDS: 2 -> 2 (0.00 %) blocks Max Waves: 17 -> 17 (0.00 %) Wait states: 0 -> 0 (0.00 %) The only difference was a manhattan31 shader. Acked-by: Timothy Arceri <[email protected]> Acked-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* panfrost: Move to use ralloc for some allocationsTomeu Vizoso2019-06-197-37/+44
| | | | | | | | | | | | | | We have some serious leaks, so plug some and also move to ralloc to limit the lifetime of some objects to that of their parent. Lots more such work to do. For some reason, this fixes: dEQP-GLES2.functional.lifetime.attach.deleted_output.texture_framebuffer Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* etnaviv: support GL_ARB_seamless_cubemap_per_textureChristian Gmeiner2019-06-192-5/+9
| | | | | | | Passes spec@amd_seamless_cubemap_per_texture@amd_seamless_cubemap_per_texture Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-By: Guido Günther <[email protected]>
* etnaviv: update headers from rnndbChristian Gmeiner2019-06-196-22/+33
| | | | | | Update to etna_viv commit a3bf0da. Signed-off-by: Christian Gmeiner <[email protected]>
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