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* radeonsi/gfx10: add a workaround for stencil HTILE with mipmappingMarek Olšák2019-07-036-12/+28
* radeonsi/gfx10: disable DCC with MSAAMarek Olšák2019-07-031-1/+6
* radeonsi/gfx10: fix GL_LINE polygon mode for decomposed primitivesMarek Olšák2019-07-035-3/+24
* radeonsi/gfx10: fix NGG GS color clampingMarek Olšák2019-07-031-0/+4
* radeonsi/gfx10: fix vertex color clamping for TESMarek Olšák2019-07-031-5/+18
* radeonsi/gfx10: unbind NGG shaders when destroyedMarek Olšák2019-07-031-0/+9
* radeonsi/gfx10: don't use the GS workaround for triangle strips w/ adjancencyMarek Olšák2019-07-031-1/+1
* radeonsi/gfx10: don't do the query buffer atomic for blit shadersMarek Olšák2019-07-031-23/+26
* radeonsi/gfx10: update spi_map if API VS (as NGG) changes and PS doesn'tMarek Olšák2019-07-031-1/+3
* radeonsi/gfx10: fix a possible hang with exp pos0 with done=0 and exec=0Marek Olšák2019-07-031-0/+8
* radeonsi/gfx10: prefetch HW GS when NGG is usedMarek Olšák2019-07-031-2/+2
* radeonsi/gfx10: fix PS exports for SPI_SHADER_32_ARMarek Olšák2019-07-031-3/+9
* radeonsi/gfx10: set DLC for loads when GLC is setMarek Olšák2019-07-031-5/+8
* radeonsi/gfx10: fix shader imagesMarek Olšák2019-07-031-2/+3
* radeonsi/gfx10: set the DCC constant encoding flagMarek Olšák2019-07-031-1/+2
* radeonsi/gfx10: fix intensity formatsMarek Olšák2019-07-035-14/+23
* radeonsi/gfx10: allocate GDS BOs for streamoutMarek Olšák2019-07-034-10/+40
* radeonsi/gfx10: make sure GDS is idle between IBsMarek Olšák2019-07-032-9/+28
* radeonsi/gfx10: implement streamoutNicolai Hähnle2019-07-034-33/+618
* radeonsi/gfx10: implement streamout-related queriesNicolai Hähnle2019-07-0312-3/+903
* radeonsi/gfx10: enable the workaround for unaligned vertex fetchNicolai Hähnle2019-07-031-1/+3
* radeonsi/gfx10: re-order the initialization order in si_compile_tgsi_mainNicolai Hähnle2019-07-031-32/+32
* radeonsi/gfx10: apply DCC MSAA blend workaroundNicolai Hähnle2019-07-031-3/+1
* radeonsi/gfx10: implement si_emit_global_shader_pointersNicolai Hähnle2019-07-031-1/+12
* radeonsi/gfx10: implement si_init_tess_factor_ringNicolai Hähnle2019-07-031-1/+4
* radeonsi/gfx10: initialize EXEC for TES-as-NGG (without geometry shader)Nicolai Hähnle2019-07-031-1/+3
* radeonsi/gfx10: use correct VGPR for instance ID in LS shaderNicolai Hähnle2019-07-031-2/+7
* radeonsi/gfx10: implement si_shader_hsNicolai Hähnle2019-07-031-7/+26
* radeonsi/gfx10: implement si_create_sampler_stateNicolai Hähnle2019-07-031-5/+10
* radeonsi/gfx10: double the number of tessellation offchip buffers per SENicolai Hähnle2019-07-031-2/+4
* radeonsi/gfx10: implement get_tess_ring_descriptorNicolai Hähnle2019-07-031-7/+14
* radeonsi/gfx10: mask DCC tile swizzle by alignmentNicolai Hähnle2019-07-032-2/+7
* radeonsi/gfx10: implement hardware MSAA resolveNicolai Hähnle2019-07-033-1/+15
* radeonsi/gfx10: fix binding on si_update_scratch_relocsNicolai Hähnle2019-07-031-3/+7
* radeonsi/gfx10: set llvm_has_working_vgpr_indexingNicolai Hähnle2019-07-031-3/+2
* radeonsi/gfx10: implement load_const_buffer_desc_fast_pathNicolai Hähnle2019-07-031-7/+14
* radeonsi/gfx10: take PRIMID from the correct output when exported by GSNicolai Hähnle2019-07-031-2/+2
* radeonsi/gfx10: change location of instance ID shader inputNicolai Hähnle2019-07-031-2/+11
* radeonsi/gfx10: set USER_DATA_ADDR offset for geometry shadersNicolai Hähnle2019-07-031-2/+8
* radeonsi/gfx10: implement si_emit_derived_tess_stateNicolai Hähnle2019-07-031-2/+6
* radeonsi/gfx10: implement si_shader_gsNicolai Hähnle2019-07-031-15/+29
* radeonsi/gfx10: implement preload_ring_buffersNicolai Hähnle2019-07-031-11/+20
* radeonsi/gfx10: implement si_set_ring_bufferNicolai Hähnle2019-07-031-2/+9
* radeonsi/gfx10: allow rectangle outputs from NGG primitive shaderNicolai Hähnle2019-07-031-0/+1
* radeonsi/gfx10: emit VGT_GS_OUT_PRIM_TYPE from draw and add it to VS_STATENicolai Hähnle2019-07-035-48/+52
* radeonsi/gfx10: NGG geometry shader PM4 and uploadNicolai Hähnle2019-07-035-29/+316
* radeonsi/gfx10: generate geometry shaders for NGGNicolai Hähnle2019-07-034-4/+439
* radeonsi/gfx10: use the correct register for image descriptor dumpingNicolai Hähnle2019-07-031-3/+5
* radeonsi/gfx10: emit GE_CNTL instead of IA_MULTI_VGT_PARAM for legacy modeNicolai Hähnle2019-07-031-7/+60
* radeonsi/gfx10: initialize GE_{MAX,MIN}_VTX_INDX/INDX_OFFSETNicolai Hähnle2019-07-031-1/+5
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