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* freedreno: add pctx->memory_barrier()Rob Clark2018-03-051-0/+8
* freedreno/ir3: cmdline compiler updates for spv shadersRob Clark2018-03-051-0/+7
* ac: add ac_build_fsign()Samuel Pitoiset2018-03-051-11/+4
* ac: add ac_build_isign()Samuel Pitoiset2018-03-051-8/+2
* ac: add ac_build_fract()Samuel Pitoiset2018-03-051-8/+5
* virgl: add offset alignment values to to v2 caps struct[email protected]2018-03-053-2/+6
* virgl: reduce some default capset limits.Dave Airlie2018-03-051-8/+8
* virgl: handle getting new capsets.Dave Airlie2018-03-051-1/+24
* radeonsi/nir: call ac_lower_indirect_derefs()Timothy Arceri2018-03-054-4/+6
* radeonsi: add chip class to compiler_ctx_stateTimothy Arceri2018-03-053-0/+4
* swr/rast: Fix macOS macro.Vinson Lee2018-03-041-2/+2
* svga: add SVGA_NEW_PRESCALE to the tracked dirty mask for gsCharmaine Lee2018-03-021-1/+2
* svga: fix blending regressionBrian Paul2018-03-021-11/+24
* svga: check svga_have_vgpu10() in svga_delete_blend_state()Brian Paul2018-03-021-1/+1
* svga: if svga_update_state() fails, skip the draw callBrian Paul2018-03-021-5/+5
* svga: let svga_update_state_retry() return a boolBrian Paul2018-03-022-6/+9
* svga: s/unsigned/boolean/ for a few local varsBrian Paul2018-03-021-6/+6
* radeonsi: fix radeon create encoder returnBoyuan Zhang2018-03-021-1/+1
* r600/cayman: fix fragcood loading recip generation.Dave Airlie2018-03-021-1/+1
* radeonsi/nir: increase values to 8 for gs fetch.Dave Airlie2018-03-011-1/+1
* radeonsi: set some context vars for nir pathTimothy Arceri2018-03-011-6/+10
* broadcom/vc5: Fix regression in the page-cache slice size alignment.Eric Anholt2018-02-281-3/+6
* r600/shader: when using images always load thread id gpr at start (v2)Dave Airlie2018-02-281-15/+7
* r600: fix whitespace in recent 1d texture commit.Dave Airlie2018-02-281-1/+1
* swr/rast: revert clip distance precisionGeorge Kyriazis2018-02-282-4/+17
* swr/rast: Faster frustum prim cullingGeorge Kyriazis2018-02-281-3/+7
* swr/rast: Consolidate TRANSLATE_ADDRESSGeorge Kyriazis2018-02-284-6/+28
* swr/rast: Code generation cleanupGeorge Kyriazis2018-02-281-15/+21
* swr/rast: Remove draw type from event definitionsGeorge Kyriazis2018-02-283-12/+8
* swr/rast: whitespace changeGeorge Kyriazis2018-02-281-1/+1
* swr/rast: Fix index buffer overfetch issue for non-indexed drawsGeorge Kyriazis2018-02-281-0/+15
* softpipe: don't iterate through PIPE_MAX_SHADER_SAMPLER_VIEWSRoland Scheidegger2018-02-281-2/+2
* r600: partly revert disabling tiling for 1d texture.Dave Airlie2018-02-281-0/+5
* nir: add lower_ldexp to nir compiler optionsTimothy Arceri2018-02-282-0/+2
* ac/radeonsi: add load_base_vertex() to the abiTimothy Arceri2018-02-281-0/+1
* radeonsi: create get_base_vertex() helperTimothy Arceri2018-02-281-14/+20
* radeonsi/nir: disable vertex_id_zero_based loweringTimothy Arceri2018-02-281-1/+0
* nvc0: collapse output slots to have adjacent registersIlia Mirkin2018-02-271-2/+12
* nvir/gm107: consider FILE_FLAGS dependencies in SchedDataCalculatorGM107Karol Herbst2018-02-261-1/+14
* nvir/gm107: iterate over all defs in SchedDataCalculatorGM107::findFirstUseKarol Herbst2018-02-261-16/+18
* radeonsi: remove 2 unused user SGPRs from merged TES-GS with 32-bit pointersMarek Olšák2018-02-264-11/+35
* radeonsi: make SI_SGPR_VERTEX_BUFFERS the last user SGPR inputMarek Olšák2018-02-264-20/+53
* radeonsi: set correct num_input_sgprs for VS prolog in merged shadersMarek Olšák2018-02-261-24/+24
* radeonsi: allow fewer input SGPRs in 2nd shader of merged shadersMarek Olšák2018-02-261-1/+5
* radeonsi: don't use struct si_descriptors for vertex buffer descriptorsMarek Olšák2018-02-266-33/+46
* r600: fix tgsi clock last settingDave Airlie2018-02-261-0/+1
* r600: add time lo/hi debugging output.Dave Airlie2018-02-262-0/+12
* radeonsi/nir: enable lowering of fpowTimothy Arceri2018-02-261-0/+1
* radeonsi/nir: fix loading of doubles for tess varyingsTimothy Arceri2018-02-261-2/+10
* radeonsi/nir: fix lds store in tcs outputs handlingTimothy Arceri2018-02-261-1/+1
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