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* swr: [rasterizer archrast] add mako templateTim Rowley2016-10-114-2/+117
* swr: [rasterizer core] disable cull for rect_listTim Rowley2016-10-111-0/+8
* swr: [rasterizer core] add support for "RAW" surface formatTim Rowley2016-10-112-0/+29
* swr: [rasterizer core] align Macrotile FIFO memory to SIMD sizeTim Rowley2016-10-114-9/+23
* swr: [rasterizer common] remove threadviz codeTim Rowley2016-10-113-94/+0
* swr: [rasterizer memory] split load/store for compile speedTim Rowley2016-10-1117-1836/+2290
* i915g: fix incorrect gl_FragCoord valueNicholas Bishop2016-10-101-1/+6
* softpipe: Cap to 2 GB on 32 bitsAxel Davy2016-10-101-0/+6
* llvmpipe: Cap to 2 GB on 32 bitsAxel Davy2016-10-101-0/+6
* nvc0: fix valid range for shader buffersSamuel Pitoiset2016-10-103-0/+3
* nvc0/ir: fix overwriting of value backing non-constant gather offsetIlia Mirkin2016-10-101-2/+2
* nv50/ir: only stick one preret per functionIlia Mirkin2016-10-101-4/+7
* radeonsi: make more use of si_have_tgsi_computeNicolai Hähnle2016-10-101-3/+1
* gallium/radeon: assign a name to LLVM output variables in debug buildsNicolai Hähnle2016-10-101-1/+6
* gallium/radeon: avoid redundant work with overlapping in/out arraysNicolai Hähnle2016-10-101-1/+4
* radeonsi: support ARB_compute_variable_group_sizeNicolai Hähnle2016-10-105-17/+53
* gallium: add missing zero-init for resource templatesRob Clark2016-10-071-0/+1
* freedreno: don't try to shadow layered texturesRob Clark2016-10-071-0/+3
* freedreno/a3xx+a4xx: fix clip-plane lowering stateRob Clark2016-10-072-0/+6
* vc4: Don't worry about partial Z/S clear if the other is already cleared.Eric Anholt2016-10-061-3/+7
* vc4: Try to fix the HW-2116 workaround.Eric Anholt2016-10-061-9/+10
* vc4: Drop dead argument from vc4_start_draw().Eric Anholt2016-10-061-3/+3
* vc4: Fix fallback to quad clears of depth in GLX.Eric Anholt2016-10-064-25/+64
* vc4: Add the format name in miptree_debug.Eric Anholt2016-10-061-2/+4
* vc4: Fix perf debug formatting on partial Z/S clear.Eric Anholt2016-10-061-1/+1
* vc4: Drop destination register when it's unused.Eric Anholt2016-10-061-1/+22
* vc4: Fix live intervals analysis for screening defs in if statements.Eric Anholt2016-10-063-5/+20
* vc4: Fix simulator when more than one vc4_screen is opened.Eric Anholt2016-10-063-3/+39
* vc4: Fix assertion fails from trying to cast non-ALU instrs to ALU.Eric Anholt2016-10-061-0/+2
* nv50/ir: fix wrong check when optimizing MAD to SHLADDSamuel Pitoiset2016-10-071-1/+1
* nvc0: dump program binary only when NV50_PROG_DEBUG is setSamuel Pitoiset2016-10-071-1/+1
* nvc0: expose ARB_compute_variable_group_sizeSamuel Pitoiset2016-10-071-2/+6
* nv50/ir: set number of threads/block for variable local sizeSamuel Pitoiset2016-10-071-0/+2
* gallium: add PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCKSamuel Pitoiset2016-10-075-0/+9
* nv50/ir: optimize sub(a, 0) to aKarol Herbst2016-10-061-0/+3
* nir: Make nir_foo_first/last_cf_node return a block insteadJason Ekstrand2016-10-062-11/+6
* svga: add svga_mksstats.h to the sources listEmil Velikov2016-10-061-0/+1
* nvc0: dump program binary when chipset has been forcedSamuel Pitoiset2016-10-051-0/+5
* radeonsi: fix texture border colors for compute shadersMarek Olšák2016-10-051-0/+12
* radeonsi: fix interpolateAt opcodes for .zw componentsMarek Olšák2016-10-051-1/+1
* radeonsi: add assertions to validate interpolation flagsMarek Olšák2016-10-051-0/+34
* radeonsi: interpolate colors after interpolation weight shufflingMarek Olšák2016-10-051-48/+48
* ddebug: dump most driver information with GALLIUM_DDEBUG=alwaysMarek Olšák2016-10-051-1/+5
* nv50/ra: let simplify return an error and handle thatKarol Herbst2016-10-051-5/+7
* virgl: Fix build regression of commit 8a943564Nicolai Hähnle2016-10-051-1/+1
* gallium/radeon: implement set_device_reset_callbackNicolai Hähnle2016-10-054-0/+40
* ddebug: add pass-through of set_device_reset_callbackNicolai Hähnle2016-10-051-0/+10
* virgl: use the new parent/child pools for transfersNicolai Hähnle2016-10-056-8/+14
* vc4: use the new parent/child pools for transfersNicolai Hähnle2016-10-055-6/+11
* freedreno: use the new parent/child pools for transfersNicolai Hähnle2016-10-055-6/+12
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