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* vc4: Add some dumping for STORE_TILE_BUFFER_GENERAL.Eric Anholt2015-01-151-1/+79
* vc4: Add dumping for the TILE_RENDERING_MODE_CONFIG packet.Eric Anholt2015-01-151-1/+70
* vc4: Fix CL dumping trying to dump too far.Eric Anholt2015-01-151-2/+2
* vc4: Fix texture type masking.Eric Anholt2015-01-151-1/+1
* vc4: Colormask should apply after all other fragment ops (like logic op).Eric Anholt2015-01-151-9/+18
* vc4: No turning unpack arguments into small immediates.Eric Anholt2015-01-151-0/+3
* vc4: Move the tests for src needing to be an A register to vc4_qir.c.Eric Anholt2015-01-153-17/+28
* vc4: Don't swap the raddr on instructions doing unpacks.Eric Anholt2015-01-151-0/+5
* vc4: Don't let pairing happen with badly mismatched unpack flags.Eric Anholt2015-01-151-0/+39
* vc4: Don't let pairing happen with badly mismatched pack flags.Eric Anholt2015-01-151-0/+39
* vc4: Fix early Z behavior on hardware.Eric Anholt2015-01-151-2/+1
* Revert "radeonsi: only set BC_OPTIMIZE_DISABLE when necessary"Michel Dänzer2015-01-152-15/+6
* freedreno/ir3: handle "holes" in inputsRob Clark2015-01-131-1/+31
* r600g: fix build failure when building the driver without LLVMMarek Olšák2015-01-121-0/+4
* vc4: Clamp the inputs to the blend equation to [0, 1].Eric Anholt2015-01-111-1/+10
* vc4: Add a little helper for clamping to [0,1].Eric Anholt2015-01-111-4/+10
* vc4: Fix up statechange management for uncompiled/compiled FS/VS.Eric Anholt2015-01-112-11/+10
* vc4: Fix clear color setup for RGB565.Eric Anholt2015-01-111-1/+4
* vc4: Avoid the save/restore of r3 for raddr conflicts, just use ra31.Eric Anholt2015-01-112-38/+11
* vc4: Allow dead code elimination of VPM reads.Eric Anholt2015-01-102-1/+44
* vc4: Cook up the draw-time VPM setup info during shader compile.Eric Anholt2015-01-104-11/+28
* vc4: Split two notions of instructions having side effects.Eric Anholt2015-01-105-4/+15
* vc4: Redo VPM reads as a read file.Eric Anholt2015-01-105-16/+16
* vc4: Fix miscalculation of the VPM space.Eric Anholt2015-01-101-1/+1
* vc4: Pack VPM attr contents according to just the size of the attribute.Eric Anholt2015-01-103-11/+9
* vc4: Restructure color packing as a series of channel replacements.Eric Anholt2015-01-104-49/+60
* vc4: Fix the no-copy-propagating-from-TLB_COLOR_READ check.Eric Anholt2015-01-101-1/+1
* vc4: Move global seqno short-circuiting to vc4_wait_seqno().Eric Anholt2015-01-102-6/+3
* freedreno/ir3: fix pos_regid > max_regRob Clark2015-01-074-41/+121
* freedreno/ir3: start on indirect gpr readsRob Clark2015-01-073-8/+146
* freedreno/ir3: make reg array dynamicRob Clark2015-01-074-13/+50
* freedreno/ir3: simplify RARob Clark2015-01-078-777/+622
* freedreno/ir3: regmask support for relative addrRob Clark2015-01-072-17/+51
* freedreno/ir3: split up ssa_srcRob Clark2015-01-071-23/+34
* freedreno/ir3: drop instr_clone() stuffRob Clark2015-01-072-49/+17
* freedreno/ir3: runtime enable RA debug for DEBUG buildsRob Clark2015-01-071-1/+6
* freedreno/ir3: handle relative addr in ir3_dumpRob Clark2015-01-071-1/+8
* freedreno/ir3: legalize vs unused sam dst componentsRob Clark2015-01-072-2/+9
* freedreno/ir3: hack for old compilerRob Clark2015-01-071-0/+23
* Revert "radeonsi: reduce the size of si_pm4_state"Marek Olšák2015-01-082-3/+12
* radeonsi: Fix crash when destroying si_screenTom Stellard2015-01-071-2/+4
* radeonsi: enable LLVM optimizations that assume no NaNs for non-compute shadersMarek Olšák2015-01-073-4/+12
* radeonsi: emit SURFACE_SYNC lastMarek Olšák2015-01-071-23/+35
* radeonsi: flush all CB/DB caches unconditionally when changing the framebufferMarek Olšák2015-01-071-11/+7
* radeonsi: change TC cache flushing strategy for texturesMarek Olšák2015-01-072-4/+6
* radeonsi: improve and fix streamout flushingMarek Olšák2015-01-073-10/+40
* radeonsi: use TC L2 for CP DMA operations with shader resources on CIKMarek Olšák2015-01-073-10/+39
* radeonsi: use TC L2 for updating descriptors on CIKMarek Olšák2015-01-072-5/+10
* radeonsi: don't use TC L2 for updating descriptors on SIMarek Olšák2015-01-072-2/+14
* radeonsi: only flush the right set of caches for CP DMA operationsMarek Olšák2015-01-079-34/+48
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