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* vc4: Don't bother de-SSAing values that aren't part of phi webs.Eric Anholt2015-08-041-15/+44
| | | | We can just support them the same way we do load_const's SSA values.
* vc4: Don't bother saturating the dst color for blending.Eric Anholt2015-08-041-8/+2
| | | | | | | | | Since we just pulled it out of the destination as 8-bit unorm, we know it's in [0, 1] already. shader-db: total instructions in shared programs: 100040 -> 98208 (-1.83%) instructions in affected programs: 14084 -> 12252 (-13.01%)
* vc4: Make r4-writes implicitly move to a temp, and allocate temps to r4.Eric Anholt2015-08-048-107/+106
| | | | | | | | | | | Previously, SFU values always moved to a temporary, and TLB color reads and texture reads always lived in r4. Instead, we can have these results just be normal temporaries, and the register allocator can leave the values in r4 when they don't interfere with anything else using r4. shader-db results: total instructions in shared programs: 100809 -> 100040 (-0.76%) instructions in affected programs: 42383 -> 41614 (-1.81%)
* vc4: Drop a dead prototype.Eric Anholt2015-08-041-8/+0
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* freedreno/a4xx: add independent blend function supportRob Clark2015-08-042-8/+10
| | | | | | needed for MRT Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: MRT supportRob Clark2015-08-0412-132/+212
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: move the half-precision logic into coreRob Clark2015-08-044-31/+38
| | | | | | | | Both a3xx and a4xx need the same logic to decide if half-precision can be used for blit shaders. So move it to core and simplify things a bit with a helper that considers all render targets. Signed-off-by: Rob Clark <[email protected]>
* freedreno: simplify/cleanup resource status trackingRob Clark2015-08-044-48/+71
| | | | | | | | | Collapse dirty/reading bools into status bitmask (and drop writing which should really be the same as dirty). And use 'used_resources' list for all tracking, including zsbuf/cbufs, rather than special casing the color and depth/stencil buffers. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix stream-out caps vec4->componentsRob Clark2015-08-041-2/+2
| | | | | | Should be in units of components, not vec4's Signed-off-by: Rob Clark <[email protected]>
* freedreno: small bit of cleanup about max rendertargetsRob Clark2015-08-0413-17/+40
| | | | | | | | We hard-coded 4 or 8 as the max in various places. Switch it all to a define since the limit will go up with a4xx (and maybe even again in the future?) Signed-off-by: Rob Clark <[email protected]>
* r600,compute: force tiling on 2D and 3D texture compute resourcesZoltan Gilian2015-08-031-2/+9
| | | | | | | To circumvent a problem occuring when LINEAR_ALIGNED array mode is selected on a TEXTURE_2D RAT. This configuration causes MEM_RAT STORE_TYPED to write to incorrect locations.
* r600g: re-enable single-sample fast clearMarek Olšák2015-08-031-6/+1
| | | | | | | Fixed by the CB_SHADER_MASK fix. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* r600g: fix the CB_SHADER_MASK setupMarek Olšák2015-08-032-4/+5
| | | | | | | | This fixes the single-sample fast clear hang. Cc: 10.6 <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* r600g: fix the single-sample fast clear setupMarek Olšák2015-08-031-2/+6
| | | | | | | No effect, but this is what we should be doing. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: flush if the memory usage for an IB is too highMarek Olšák2015-08-022-0/+17
| | | | | | | Picked from the amdgpu branch. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* Revert "gallium/radeon: re-enable unsafe math for graphics shaders"Marek Olšák2015-08-011-4/+0
| | | | | | This reverts commit 8559f6ce62a9d5b52fa8189ba2352cd48bdabccf. It causes hangs in DOTA 2 Reborn.
* radeonsi: copy *8_SNORM bits exactly in resource_copy_regionMarek Olšák2015-07-311-1/+3
| | | | | | | | | | Disabling the FP16 mode didn't help. If needed, we can use this trick for blits too, but not for scaled blits. + 4 piglits Reviewed-by: Michel Dänzer <[email protected]>
* r600g: early exit in r600_clear if there's nothing to doMarek Olšák2015-07-311-0/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: early exit in si_clear if there's nothing to doMarek Olšák2015-07-311-0/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix a regression since the resource_copy_region cleanupMarek Olšák2015-07-311-1/+1
| | | | | | | | | Broken since: 46b2b3b - radeonsi: don't change pipe_resource in resource_copy_region Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91444 Reviewed-and-Tested-by: Michel Dänzer <[email protected]>
* radeonsi: fix broken st/nine from merging tessellationMarek Olšák2015-07-311-2/+7
| | | | st/nine uses GENERIC slots greater than 60.
* radeonsi: move CP DMA functions to their own fileMarek Olšák2015-07-316-236/+274
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add a debug flag that disables printing ISA in shader dumpsMarek Olšák2015-07-313-9/+13
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* radeonsi: add a debug flag that disables printing TGSI in shader dumpsMarek Olšák2015-07-313-1/+3
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: add a debug flag that disables printing the LLVM IR in shader dumpsMarek Olšák2015-07-316-29/+29
| | | | This is for shader-db and should reduce size of shader dumps.
* radeonsi: store shader disassemblies in memory for future usersMarek Olšák2015-07-317-17/+18
| | | | | This will be used by the new ddebug pipe. I'm including it now to avoid conflicts with other patches.
* radeonsi: don't use llvm.AMDIL.fraction for FRC and DFRACMarek Olšák2015-07-311-4/+16
| | | | | | | | There are 2 reasons for this: - LLVM optimization passes can work with floor - there are patterns to select v_fract from floor anyway There is no change in the generated code.
* gallium/radeon: re-enable unsafe math for graphics shadersMarek Olšák2015-07-311-0/+4
| | | | | | | | | | | | | | | | This reverts commit 4db985a5fa9ea985616a726b1770727309502d81. The grass no longer disappears, which was the reason the commit was reverted. This might affect tessellation. We'll see. Totals from affected shaders: SGPRS: 151672 -> 150232 (-0.95 %) VGPRS: 90620 -> 89776 (-0.93 %) Code Size: 3980472 -> 3920836 (-1.50 %) bytes LDS: 67 -> 67 (0.00 %) blocks Scratch: 1357824 -> 1202176 (-11.46 %) bytes per wave Reviewed-by: Tom Stellard <[email protected]>
* gallium/radeon: don't use rsq_actionMarek Olšák2015-07-311-7/+3
| | | | Reviewed-by: Dave Airlie <[email protected]>
* gallium/radeon: move r600-specific code to r600gMarek Olšák2015-07-312-152/+150
| | | | Reviewed-by: Tom Stellard <[email protected]>
* gallium/radeon: remove unused variables and old commentsMarek Olšák2015-07-314-35/+0
| | | | Reviewed-by: Dave Airlie <[email protected]>
* gallium/radeon: remove build_intrinsic and build_tgsi_intrinsicMarek Olšák2015-07-314-108/+58
| | | | | | duplicated now Reviewed-by: Dave Airlie <[email protected]>
* gallivm: add LLVMAttribute parameter to lp_build_intrinsicMarek Olšák2015-07-312-9/+9
| | | | | | This will help remove some duplicated code from radeon. Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: completely rework updating descriptors without CP DMAMarek Olšák2015-07-314-271/+128
| | | | | | | | | | | | | | | | | | | | The patch has a better explanation. Just a summary here: - The CPU always uploads a whole descriptor array to previously-unused memory. - CP DMA isn't used. - No caches need to be flushed. - All descriptors are always up-to-date in memory even after a hang, because CP DMA doesn't serve as a middle man to update them. This should bring: - better hang recovery (descriptors are always up-to-date) - better GPU performance (no KCACHE and TC flushes) - worse CPU performance for partial updates (only whole arrays are uploaded) - less used IB space (no CP_DMA and WRITE_DATA packets) - simpler code - hopefully, some of the corruption issues with SI cards will go away. If not, we'll know the issue is not here. Reviewed-by: Michel Dänzer <[email protected]>
* vc4: Lower uniform loads to scalar in NIR.Eric Anholt2015-07-302-31/+81
| | | | | This also moves the vec4-to-byte-addressing math into NIR, so that algebraic has a chance at it.
* vc4: Move some FS input lowering into NIR.Eric Anholt2015-07-302-35/+50
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* vc4: Move program keys to the header file.Eric Anholt2015-07-302-47/+49
| | | | | I want to be able to inspect them from other files for lowering passes in NIR.
* vc4: Lower NIR inputs to scalar as well.Eric Anholt2015-07-302-4/+44
| | | | | For now this is just scalarizing, but it also means we'll get to dump a bunch of QIR-based lowering in a moment.
* vc4: Start adding a NIR-based output lowering pass.Eric Anholt2015-07-304-7/+137
| | | | | | For now, this just splits up store_output intrinsics to be scalars, and drops unused outputs in the coordinate shader. My goal is to be able to drop a bunch of my VC4-specific optimization by letting NIR handle it.
* vc4: Mark our shaders as single-threaded.Eric Anholt2015-07-302-0/+6
| | | | | I had my understanding of this bit flipped. We're using the full register space, so we need to say so.
* vc4: Avoid leaking indirect array access UBOs.Eric Anholt2015-07-301-0/+2
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* vc4: Avoid overflowing various static tables.Eric Anholt2015-07-304-4/+4
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* vc4: Fix return values from recent validation changes.Eric Anholt2015-07-301-4/+4
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* radeonsi: enable GL4.1 and update documentation (v2)Dave Airlie2015-07-301-1/+1
| | | | | | | | | | This enables GL4.1 for radeonsi, and updates the docs in the correct places. v2: enable only for llvm 3.7 which has fixes in place. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: add GS multiple streams support (v2)Dave Airlie2015-07-306-39/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | This is the final piece for ARB_gpu_shader5, The code is based on the r600 code from Glenn Kennard, and myself. While developing this, I'm not 100% sure of all the calculations made in the GS registers, this is why the max_stream is worked out there and used to limit the changes in registers. Otherwise my initial attempts either regressed GS texelFetch tests or primitive-id-restart. The current code has no regressions in piglit. This commit doesn't enable ARB_gpu_shader5, since that just bumps the glsl level to 4.00, so I'll just do a separate patch for 4.10. v1.1: fix bug introduced in rebase. v2: Address Marek's review comments, remove my llvm stream code for simpler C, move gsvs_ring and gs_next_vertex to arrays. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* svga: scons: remove unused HAVE_SYS_TYPES_H defineEmil Velikov2015-07-291-1/+0
| | | | | | | | | There isn't a single instance in mesa that mentions HAVE_SYS_TYPES_H, other than this file. Cc: Jose Fonseca <[email protected]> Acked-by: Brian Paul <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* nvc0/ir: cache vertex out base so that we don't recompute againIlia Mirkin2015-07-291-8/+15
| | | | | | | | The global CSE pass stinks and is unable to pull this out. Easy enough to handle it here and avoid generating unnecessary special register loads (which can allegedly be quite slow). Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: output base for reading is based on laneidIlia Mirkin2015-07-291-0/+25
| | | | | | | | | | | PFETCH retrieves the address for incoming vertices, not output vertices in TCS. For output vertices, we must use the laneid as a base. Fixes barrier piglit test, which was failing for entirely non-barrier reasons, but rather that it was (a) trying to draw multiple patches and (b) the incoming patch size was not the same as the outgoing patch size. Signed-off-by: Ilia Mirkin <[email protected]>
* radeon: add support for streams to the common streamout code. (v2)Dave Airlie2015-07-296-15/+50
| | | | | | | | | | | | This adds to the common radeon streamout code, support for multiple streams. It updates radeonsi/r600 to set the enabled mask up. v2: update for changes in previous patch. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeon: move streamout buffer config to streamout enable function. (v2)Dave Airlie2015-07-292-9/+15
| | | | | | | | | | This will be used here later. v2: update atom sizes add check for old vs new enabled mask Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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