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* radeon/llvm: add missing cases for BREAK/CONTINUEVadim Girlin2012-05-082-0/+3
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for AHSR/LSHR/LSHL instructionsVadim Girlin2012-05-084-0/+53
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for TXQ/TXF/DDX/DDY instructionsVadim Girlin2012-05-085-4/+43
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for VertexID, InstanceIDVadim Girlin2012-05-083-0/+50
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: fix live-in handling for inputsVadim Girlin2012-05-082-2/+3
| | | | | | Set the input registers as live-in for entry basic block. Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for v4i32Vadim Girlin2012-05-084-5/+20
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: fix ABS_i32 instruction loweringVadim Girlin2012-05-081-2/+2
| | | | | | Swap source operands. Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: use integer comparison for IFVadim Girlin2012-05-081-2/+4
| | | | | | | Replacing "float equal to 1.0f" with "int not equal to 0". This should help for further optimization of boolean computations. Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: use bitcasts for integersVadim Girlin2012-05-083-5/+73
| | | | | | | | | We're using float as default type, so basically for every instruction that wants other types for dst/src operands we need to perform the bitcast to/from default float. Currently bitcast produces no-op MOV instruction, will be eliminated later. Signed-off-by: Vadim Girlin <[email protected]>
* r600g: Fix out of tree builds that use the LLVM backendTom Stellard2012-05-071-1/+1
| | | | https://bugs.freedesktop.org/show_bug.cgi?id=49567
* radeon/llvm: Remove references to DebugFlag and isCurrentDebugType()Tom Stellard2012-05-074-22/+3
| | | | | | | These weren't being used at all and they were causing build failures when LLVM was built with NDEBUG defined and mesa was not. https://bugs.freedesktop.org/show_bug.cgi?id=49110
* nv50: handle VP without inputsMarcin Slusarz2012-05-071-0/+11
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* nvc0/ir: allow abs,neg source modifiers with ceil,floor,truncChristoph Bumiller2012-05-061-0/+3
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* nv50/ir/opt: don't lose saturation in tryCollapseChainedMULsChristoph Bumiller2012-05-061-2/+3
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* nvc0/ir: fix lowering of textureGradChristoph Bumiller2012-05-063-12/+13
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* nouveau: fix nouveau_scratch_runout_release bo count underflowChristoph Bumiller2012-05-061-1/+3
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* nv50: fix typo causing NULL-deref in nv50_resource_resolveChristoph Bumiller2012-05-041-1/+1
| | | | Introduced in b328949a37fee7b0f68ed3e068ffc4426c083042.
* nv50/ir: move expansion of IMUL to later stage and handle memory operandsChristoph Bumiller2012-05-044-17/+51
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* nv50: implement stream outputChristoph Bumiller2012-05-0412-33/+468
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* nv50: enable array texturesChristoph Bumiller2012-05-042-3/+4
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* svga: specify 4-byte aligned vertex elementsBrian Paul2012-05-041-1/+2
| | | | | | | We haven't found a case where this is needed, but it would be prudent for some hosts, per Jose. Reviewed-by: José Fonseca <[email protected]>
* r600g/llvm: Mask write of pred_inst in llvm_if()Tom Stellard2012-05-031-0/+1
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* r600g/llvm: Lower ULT A, B, C to SETGT_UINT A, C, BTom Stellard2012-05-031-0/+7
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* r600g: Print integer values of literal constants in shader dumpsTom Stellard2012-05-031-1/+2
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* r600g: Add support for reading BREAK_LOGICALZ_i32 from bytestreamTom Stellard2012-05-032-0/+5
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* r600g/llvm: Don't duplicate R600 intrinsics installed by LLVMTom Stellard2012-05-034-0/+26
| | | | | | | At this point, in order for OpenCL to work correctly with r600g, OpenCL specific intrinsics need to be defined in the LLVM tree. So, we need to check for these intrinsics in the LLVM include directory to make sure not to re-define them.
* r600g: Fix the evergreen offset/end register definitionsTom Stellard2012-05-021-9/+5
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* radeon/llvm: Fix MachineInstr dumpTom Stellard2012-05-022-8/+9
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* r600g: fixed the bug with VTX fetches in TEX clauses for evergreenAdam Rak2012-05-021-7/+6
| | | | Signed-off-by: Tom Stellard <[email protected]>
* r600g: Add support for reading vertex fetches from bytestreamTom Stellard2012-05-021-0/+37
| | | | Signed-off-by: Tom Stellard <[email protected]>
* r600g: Add support for reading native instructions from the LLVM bytestreamTom Stellard2012-05-021-0/+10
| | | | Signed-off-by: Tom Stellard <[email protected]>
* r600g: Add FC_NATIVE instructionTom Stellard2012-05-023-0/+20
| | | | | | | This is a pseudo instruction that enables the LLVM backend to encode instructions and pass it through r600_bytecode_build() Signed-off-by: Tom Stellard <[email protected]>
* r600g: bypass alpha for integer types (v2)Dave Airlie2012-05-024-2/+18
| | | | | | | | | | | | This moves the alpha test control to derived state and disables alpha testing for integer fbs. fbo-blending test in piglit gets further when we do this (not a pass but less fail). v2: drop the fb_sx_alpha_test_control Signed-off-by: Dave Airlie <[email protected]>
* gallivm: Added lp_build_const_mask_aos_swizzledJames Benton2012-05-021-9/+1
| | | | | | | | | | Allows the creation of const aos masks which have the mask swizzled to match the correct format. Updated existing mask creation code to use the swizzled version where necessary (tgsi register masks and llvmpipe aos blending). Signed-off-by: José Fonseca <[email protected]>
* llvmpipe: add masking support to aos blendJames Benton2012-05-023-6/+35
| | | | Signed-off-by: José Fonseca <[email protected]>
* llvmpipe: Added support for color masks in AoS blending.James Benton2012-05-024-33/+58
| | | | Signed-off-by: José Fonseca <[email protected]>
* radeon/llvm: Fix build for updated LLVM 3.1 release branchTom Stellard2012-05-012-18/+18
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* softpipe: use any_swizzle() helper in sp_tex_sample.cBrian Paul2012-05-011-8/+15
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* softpipe: whitespace, comment clean-ups in sp_tex_sample.cBrian Paul2012-05-011-26/+32
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* softpipe: implement coord clamping for texel fetches (TXF)Brian Paul2012-05-011-14/+31
| | | | | | | | | | The GL spec says out of bounds fetches produce undefined results. Use clamping to avoid failed assertions or crashes. Fixes failed assertion in https://bugs.freedesktop.org/show_bug.cgi?id=49125 but the test still fails. Reviewed-by: Jose Fonseca <[email protected]>
* radeon/llvm: Add subtarget feature: DumpCodeTom Stellard2012-05-015-6/+9
| | | | | | With this feature enabled, the LLVM backend will dump the MachineIntrs prior to emitting code. The mesa env variable R600_DUMP_SHADERS will enable this feature in the backend.
* r600g/llvm: Remove unnecessary dynamic castsDragomir Ivanov2012-04-301-5/+5
| | | | | | | When the result of dynamic_cast is not checked, it can be replaced with static_cast Signed-off-by: Tom Stellard <[email protected]>
* r600g/llvm: Add pattern for llvm.AMDGPU.kill v2Dragomir Ivanov2012-04-302-1/+6
| | | | Signed-off-by: Tom Stellard <[email protected]>
* r600g/llvm: Fix handling of MASK_WRITE instructionsTom Stellard2012-04-302-1/+3
| | | | | | We can't delete MASK_WRITE instructions from the program, because this will cause instructions being masked by MASK_WRITE to be marked dead and then deleted in the dce pass.
* radeon/llvm: Use a custom emit function for TGSI_OPCODE_KILTom Stellard2012-04-301-1/+16
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* svga: add cases for recently added PIPE_CAP queriesBrian Paul2012-04-301-0/+3
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* nv50,nvc0: fix depth/stencil resolveChristoph Bumiller2012-04-295-56/+206
| | | | | Cannot sample depth/stencil with a single view, and needed to use different shader code for nve4.
* nvc0/ir/opt: INTERP does not support JOINChristoph Bumiller2012-04-291-0/+2
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* nv50/ir/opt: try to convert ABS(SUB) to SADChristoph Bumiller2012-04-297-16/+179
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* nvc0/ir: try to use the optimal texture op modeChristoph Bumiller2012-04-291-3/+15
| | | | | Don't really know what they are yet but for groups of textures, the last one should use mode "p" and the others "t".
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