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* radeonsi: Enable geometry shaders with LLVM 3.4.1Tom Stellard2014-05-094-9/+13
| | | | | | Reviewed-by: Michel Dänzer <[email protected]> CC: "10.1 10.2" <[email protected]>
* radeonsi: Don't use anonymous struct trick in atom trackingAdam Jackson2014-05-086-10/+10
| | | | | | | | I'm somewhat impressed that current gccs will let you do this, but sufficiently old ones (including 4.4.7 in RHEL6) won't. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* llvmpipe: change LP_MAX_SHADER_INSTRUCTIONS limit definition.Roland Scheidegger2014-05-081-1/+3
| | | | | | | | | | When the limit was changed to be defined in terms of LP_MAX_SHADER_VARIANTS (75f1fea14f524ef05e980d825fda3ae226ae2ffe) when it was increased, this inadvertently lowered the limit in some branches (that have a lower LP_MAX_SHADER_VARIANTS number) when merged. So, make sure the limit is always at least the number it once was. Reviewed-by: Jose Fonseca <[email protected]>
* nv50/ir/gk110: fix set with f32 destIlia Mirkin2014-05-071-0/+3
| | | | | | | | | Should fix comparison opcodes like SGE/SLT/etc which expected a float to be returned. These were previously getting integer 0/-1 values. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Cc: 10.2 <[email protected]>
* nv50/ir: allow load propagation when flags are definedIlia Mirkin2014-05-071-3/+4
| | | | | | | | | The old condition disallowed load propagation any time flags were defined, even with e.g. set and a constbuf reference. The new condition disallows it only with immediate propagation. (There are no opcodes that set the condition flag and have an immediate argument.) Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: add a cap for supporting 4-offset TG4 opcodesIlia Mirkin2014-05-0712-6/+18
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* svga: add switch case for PIPE_SHADER_CAP_PREFERRED_IR, remove default caseBrian Paul2014-05-071-8/+10
| | | | | | | Remove default switch case so we're warned of missing cases at compile time. Reviewed-by: José Fonseca <[email protected]>
* radeonsi: implement ARB_texture_cube_map_arrayMarek Olšák2014-05-063-6/+47
| | | | | | | | No LLVM changes needed. Reviewed-by: Michel Dänzer <[email protected]> v2: updated GL3.txt and relnotes
* nv50,nvc0: add X8Z24_UNORM, fix stencil-only formatsIlia Mirkin2014-05-041-3/+9
| | | | | | | S8_UINT will become useful when ARB_texture_stencil8 becomes supported by mesa. The other stencil formats are needed for ARB_stencil_texturing. Signed-off-by: Ilia Mirkin <[email protected]>
* radeonsi: add support for Mullins asics.Samuel Li2014-05-022-0/+9
| | | | | | | | | | | v2: name defaults to kabini for older llvm v3: fix llvm version check Signed-off-by: Samuel Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* nouveau: add ARB_buffer_storage supportIlia Mirkin2014-05-0210-5/+112
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nouveau: remove cb_dirty, it's never usedIlia Mirkin2014-05-022-4/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: treat non-linear 2DRect textures the same as 2DIlia Mirkin2014-05-021-1/+1
| | | | | | | This fixes textureGather(2DRect) piglit tests, and does not appear to have any adverse effects. Signed-off-by: Ilia Mirkin <[email protected]>
* radeon/compute: Implement PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCYTom Stellard2014-04-291-0/+7
| | | | | | | | | | | | Igor Gnatenko: v2: in define RADEON_INFO_MAX_SCLK use 0x1a instead of 0x19 (upstream changes) Bruno Jiménez: v3: Convert the frequency to MHz from kHz after getting it in 'do_winsys_init' Signed-off-by: Igor Gnatenko <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* nvc0/ir: offset appears to come before the Z refIlia Mirkin2014-04-281-1/+3
| | | | | | | | Fixes textureGatherOffset when used with a shadow sampler. Also verified against blob compiler with textureLodOffset manually (no piglit tests for texture[Lod]Offset + shadow samplers). Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: change texture offsets to ValueRefs, allow nonconstIlia Mirkin2014-04-288-20/+61
| | | | | | | This allows us to have non-constant offsets for textureGatherOffset and textureGatherOffsets. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: do constant folding of extbf/insbfIlia Mirkin2014-04-281-1/+66
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add support for MUL_HI tgsi opcodesIlia Mirkin2014-04-281-1/+12
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add support for new bitfield manipulation opcodesIlia Mirkin2014-04-287-4/+127
| | | | | | | | | | This adds support for: IBFE, UBFE, BFI, LSB, IMSB, UMSB, BREV, POPC Which are all required for ARB_gs5 support. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: fetch shadow value from proper place for TG4 cube arrayIlia Mirkin2014-04-261-1/+4
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: set gatherComp for non-shadow targetsIlia Mirkin2014-04-261-0/+2
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: set instance count based on the GS_INVOCATIONS propertyIlia Mirkin2014-04-261-3/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add support for INVOCATIONID system valueIlia Mirkin2014-04-263-2/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add support for SAMPLEMASK sysvalIlia Mirkin2014-04-265-0/+8
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: add support for PIPE_CAP_SAMPLE_SHADINGIlia Mirkin2014-04-2615-14/+131
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: add support for PIPE_CAP_SAMPLE_SHADINGIlia Mirkin2014-04-2614-8/+107
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: add basic support for ARB_sample_shadingIlia Mirkin2014-04-2612-0/+12
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: fix clearing of individual color buffers in a fbRoland Scheidegger2014-04-256-163/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GL (3.0) allows you to clear individual color buffers in a fb. In fact for fbs containing both int and float/normalized color buffers this is required (because the clearing values are otherwise undefined if applied to all buffers). The gallium interface was changed a while ago, but llvmpipe ignored it (hence doing such individual clears always resulted in clearing all buffers, plus some assorted asserts due to the mixed fbs). So change the clear command to indicate the buffer to be cleared. Also, because indicating the buffer to be cleared would have made lp_rast_arg_cmd larger which is unacceptable (we're trying to shrink it some day) allocate the clear value in the scene and just pass a pointer. There's several advantages and disadvantages here: + clearing individual buffers works (we could also actually bin such clears now if they'd come through clear_render_target() if the surface is in the current fb, though we didn't do this before for the single rb case and still don't try). + since there's one clear per rb, we do the format conversion in setup rather than per bin. Aside from the (drop in the ocean...) performance advantage this means that clearing to very small values (that is, denormal when converted to the format) should work for small float (fp16 etc.) formats, as the util code couldn't handle it correctly before (because cpu denorms are disabled when executing the bin commands, screwing up the magic conversion and flushing the values to 0, though this was not verified). - there's some overhead for traditional old-style clear-all MRT cases, since there's one rast clear command per rb instead of one for all rbs. This fixes https://bugs.freedesktop.org/show_bug.cgi?id=76976. v2: get rid of the ugly manual memcpy stuff and just use union util_color. This is 32 bytes instead of 16 but as the allocation is per scene we can live with those additional 16 bytes (and the additional 128 bytes in the setup context), which makes the code much more obvious. Suggested by Brian. Reviewed-by: Brian Paul <[email protected]>
* gallium/util: use ui[4] instead of ui in union util_colorRoland Scheidegger2014-04-259-18/+18
| | | | | | | | util_color often merely represents a collection of bytes, however it is inconvenient if those bytes can only be accessed as floats/doubles for int formats exceeding 32bits. (Note that since rgba8 formats use one uint, not 4 bytes, hence the byte and short member were left as is.)
* llvmpipe: (trivial) use correct LP_MIN_VECTOR_ALIGN define for alignment.Roland Scheidegger2014-04-251-1/+1
| | | | | | Currently it's the same value. Reviewed-by: Brian Paul <[email protected]>
* r600g: fix hang on RV740 by using DX_RASTERIZATION_KILL instead of SX_MISCMarek Olšák2014-04-255-7/+27
| | | | | | | | Changing SX_MISC hangs RV740. When we're at it, let's use DX_RASTERIZATION_KILL on all R700 and later chipsets. Cc: 10.0 10.1 [email protected] Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix for an MSAA hang on RV770Marek Olšák2014-04-253-1/+12
| | | | | Cc: 10.0 10.1 [email protected] Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix for broken CULL_FRONT behavior on R6xxMarek Olšák2014-04-254-61/+64
| | | | | Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix for HTILE on R6xxMarek Olšák2014-04-251-0/+6
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix buffer copying on R600-R700Marek Olšák2014-04-251-0/+6
| | | | | | | This fixes broken rendering in DOTA 2. Cc: 10.0 10.1 [email protected] Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix flushing on RV670, RS780, RS880 againMarek Olšák2014-04-251-0/+9
| | | | | Cc: 10.0 10.1 [email protected] Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix MSAA resolve on R6xx when the destination is 1D-tiledMarek Olšák2014-04-251-0/+6
| | | | | Cc: 10.0 10.1 [email protected] Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix edge flags and layered rendering on R600-R700Marek Olšák2014-04-251-2/+4
| | | | | | | We forgot to set these bits. Cc: 10.1 [email protected] Reviewed-by: Alex Deucher <[email protected]>
* r300g: don't crash when getting NULL colorbuffersMarek Olšák2014-04-254-29/+60
| | | | Cc: [email protected]
* r300g: fix runtime warning after winsys cleanupMarek Olšák2014-04-251-1/+0
| | | | | | Broken by: b2238b3452b0bcf3c1216c20c9918f9f0664b464 winsys/radeon: remove cs_write_reloc, add simpler cs_get_reloc
* radeonsi: implement GL_ARB_vertex_type_10f_11f_11f_revMarek Olšák2014-04-251-0/+6
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* llvmpipe: Advertise GLSL 3.30.José Fonseca2014-04-241-1/+1
| | | | | | | | | | According to Roland all TGSI support is there in theory. In practice there are a few piglit failures and crashes, as this hadn't been tested before. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* freedreno/a3xx: fix TOTALATTRTOVSRob Clark2014-04-234-1/+7
| | | | | | | | | In cases where varying fetches are optimized away (just pass-through in vertex shader, but unused in fragment shader) we need to calculate the correct TOTALATTROVS based on the actual number of varyings fetched, otherwise lockup. Signed-off-by: Rob Clark <[email protected]>
* radeonsi: Fix calculation of number of banks for SIMichel Dänzer2014-04-223-16/+20
| | | | | | | | | | | | The way cik_num_banks() was calculating the index only makes sense for the CIK specific macrotile mode array. For SI, we need to use the tile mode index directly. This happened to work most of the time because most of the SI tiling modes use the same number of banks. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* svga: move draw debug code into separate functionBrian Paul2014-04-211-123/+135
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* nouveau/codegen: add missing values for OP_TXLQ into the target arraysIlia Mirkin2014-04-192-7/+9
| | | | | | | | | | Also rework things so that if someone were to add an opcode without adjusting the values in these arrays, there will be a compilation error. This fixes a few quadop-related piglit regressions since commit d5faf8e78603. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: change logic for centering of eng2d blit when downsamplingIlia Mirkin2014-04-191-2/+2
| | | | | | | | We want to center the sample. The old code may have been correct given the limited values of ms_x/y, but the new logic should be more intuitive. Note that ms_x can only be 1/2 and ms_y can only be 0/1. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: use 2d blit when src/dst have same number of samplesIlia Mirkin2014-04-191-4/+4
| | | | | | | | | | | The 2D engine should be usable in more cases, but this fixes MS blits between textures with the same MS settings. Otherwise a single sample is selected to be the target texel value. This allows other tests to work that render to a RB and then blit that to a texture for input into a shader that uses sampler2DMS to verify it. Signed-off-by: Ilia Mirkin <[email protected]>
* radeonsi: fix num banks selection on SI for dma setup (v2)Alex Deucher2014-04-183-24/+19
| | | | | | | | | | | | The number of banks varies based on the tile mode index just like CIK. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=77533 v2: fix ordering for nbanks calculation for consistency Signed-off-by: Alex Deucher <[email protected]>
* r600g,radeonsi: don't skip the context flush if a fence should be returnedMarek Olšák2014-04-182-2/+2
| | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77589
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