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* nv50: avoid crash on updating RASTERIZE_ENABLE stateEmil Velikov2013-06-191-0/+10
| | | | | | | | When doing blit using the 3D engine, the rasterizer cso may be NULL. Ported from nvc0 commit 8aa8b0539. Signed-off-by: Emil Velikov <[email protected]>
* Revert "draw: clear the draw buffers in draw"Zack Rusin2013-06-176-9/+10
| | | | | | | | | | | This reverts commit 41966fdb3b71c0b70aeb095e0eb3c5626c144a3a. While it's a lot cleaner it causes regressions because the draw interface is always called from the draw functions of the drivers (because the buffers need to be mapped) which means that the stream output buffers endup being cleared on every draw rather than on setting. Signed-off-by: Zack Rusin <[email protected]>
* llvmpipe: fixes for conditional renderingRoland Scheidegger2013-06-184-36/+86
| | | | | | | | | | honor render_condition for clear_render_target and clear_depth_stencil. Also add minimal support for occlusion predicate, though it can't be active at the same time as an occlusion query yet. While here also switchify some large if-else (actually just mutually exclusive if-if-if...) constructs. Reviewed-by: Jose Fonseca <[email protected]>
* gallium: add condition parameter to render_conditionRoland Scheidegger2013-06-1831-23/+60
| | | | | | | | | | | | | For conditional rendering this makes it possible to skip rendering if either the predicate is true or false, as supported by d3d10 (in fact previously it was sort of implied skip rendering if predicate is false for occlusion predicate, and true for so_overflow predicate). There's no cap bit for this as presumably all drivers could do it trivially (but this patch does not implement it for the drivers using true hw predicates, nvxx, r600, radeonsi, no change is expected for OpenGL functionality). Reviewed-by: Jose Fonseca <[email protected]>
* ilo: construct depth/stencil command in create_surface()Chia-I Wu2013-06-186-271/+368
| | | | | | | | | | Add ilo_gpe_init_zs_surface() to construct 3DSTATE_DEPTH_BUFFER 3DSTATE_STENCIL_BUFFER 3DSTATE_HIER_DEPTH_BUFFER at surface creation time. This allows fast state emission in draw_vbo().
* gallium: replace bswap_32 calls with util_bswap32Jonathan Gray2013-06-174-9/+7
| | | | | | | | | byteswap.h and bswap_32 aren't portable, replace them with calls to gallium's util_bswap32 as suggested by Mark Kettenis. Lets these files build on OpenBSD. Signed-off-by: Jonathan Gray <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* draw: clear the draw buffers in drawZack Rusin2013-06-176-10/+9
| | | | | | | | | | Moves clearing of the draw so target buffers to the draw module. They had to be cleared in the drivers before which was quite messy. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* ilo: add pipe-based copy method to ilo_blitterChia-I Wu2013-06-172-5/+25
| | | | It enables accelerated resource_copy_region() when blt-based method fails.
* ilo: add BLT-based blitting methods to ilo_blitterChia-I Wu2013-06-174-495/+847
| | | | | | Port BLT code in ilo_blit.c to BLT-based blitting methods of ilo_blitter. Add BLT-based clears. The latter is verifed with util_clear(), but it is not in use yet.
* ilo: replace util_blitter by ilo_blitterChia-I Wu2013-06-177-103/+363
| | | | | ilo_blitter is just a wrapper for util_blitter for now. We will port BLT code to ilo_blitter shortly.
* ilo: fix for half-float vertex arraysChia-I Wu2013-06-151-1/+14
| | | | | Commit 6fe0453c339b6e894e0ee8d2200e7638a43ed21e broke half-float vertex arrays. This reverts a part of that commit, and explains why.
* ilo: add some assertions to help debuggingChia-I Wu2013-06-141-1/+23
| | | | | | Assert that we do not support user vertex/index/constant buffers. Issue a warning when a sampler view is created for a resource without PIPE_BIND_SAMPLER_VIEW.
* ilo: silence a compiler warningChia-I Wu2013-06-141-0/+2
| | | | The path should never be hit.
* ilo: mapping a resource may make some states dirtyChia-I Wu2013-06-134-9/+112
| | | | | | | | | When a resource is busy and is mapped with PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE, the underlying bo is replaced. We need to mark states affected by the resource dirty. With this change, we no longer have to emit vertex buffers and index buffer unconditionally.
* ilo: bump up PIPE_CAP_GLSL_FEATURE_LEVEL to 140Chia-I Wu2013-06-131-1/+1
| | | | With UBO and TBO support, we are supposedly good to claim GLSL 1.40.
* ilo: initialize dirty flags in ilo_init_states()Chia-I Wu2013-06-132-2/+2
| | | | | Now that we have a function to initialize states, initialize dirty flags there too.
* ilo: re-emit states that involve resourcesChia-I Wu2013-06-134-21/+23
| | | | | | | Even with hardware contexts, since we do not pin resources, we have to re-emit the states so that the resources are referenced (by cp->bo) and their offsets are updated in case they are moved. This also allows us to elimiate cp flush in is_bo_busy().
* ilo: fix for util_blitter_clear() changesChia-I Wu2013-06-131-4/+1
| | | | It has been broken since 17350ea979b883662573dac136cd9efb49938210.
* r600g: upsample and downsample MSAA resources for transfersMarek Olšák2013-06-131-79/+141
| | | | | | | | | | | We did downsample (=resolve) MSAA resources to make ReadPixels work with MSAA GLX visuals, which was enough for read-only color-only transfers. This commit makes write color transfers and depth-stencil transfers work in a similar manner. It does downsampling in transfer_map and upsampling in transfer_unmap. Reviewed-by: Brian Paul <[email protected]>
* gallium/u_blitter: make clearing independent of the colorbuffer formatMarek Olšák2013-06-133-6/+3
| | | | | | | There isn't any difference between 32_FLOAT and 32_*INT in vertex fetching. Both of them don't do any format conversion. Reviewed-by: Brian Paul <[email protected]>
* gallium/u_blitter: make clearing independent of the number of bound colorbuffersMarek Olšák2013-06-133-3/+2
| | | | | | We can use the fragment shader TGSI property WRITES_ALL_CBUFS. Reviewed-by: Brian Paul <[email protected]>
* util: new util_fill_box helperRoland Scheidegger2013-06-131-29/+25
| | | | | | | | | Use new util_fill_box helper for util_clear_render_target. (Also fix off-by-one map error.) v2: handle non-zero z correctly in new helper Reviewed-by: Jose Fonseca <[email protected]>
* ilo: update winsys interfaceChia-I Wu2013-06-121-7/+14
| | | | | | The motivation is to kill tiling and pitch in struct intel_bo. That requires us to make tiling and pitch not queryable, and be passed around as function parameters.
* ilo: get rid of function tables in winsysChia-I Wu2013-06-1214-90/+88
| | | | | We are moving toward making struct intel_bo alias drm_intel_bo. As a first step, we cannot have function tables.
* ilo: access bo size directlyChia-I Wu2013-06-121-2/+2
| | | | buf->bo_size is readily avaiable, no need to go via buf->bo->get_size().
* ilo: remove unnecessary tex_set_bo/buf_set_boChia-I Wu2013-06-121-42/+18
| | | | Merge the bodies to tex_create_bo/buf_create_bo respectively.
* nvc0: fix up video buffer alignment requirementsMaarten Lankhorst2013-06-081-5/+3
| | | | Signed-off-by: Maarten Lankhorst <[email protected]>
* freedreno: better scissor fixRob Clark2013-06-085-28/+43
| | | | | | Actually respect rasterizer state. Signed-off-by: Rob Clark <[email protected]>
* freedreno: gmem bypassRob Clark2013-06-087-30/+168
| | | | | | | | | | | | | The GPU (at least a3xx, but I think also a2xx) can render directly to memory, bypassing tiling. Although it can't do this if blend, depth, and a few other features of the pipeline are enabled. This direct memory mode can be faster for some sorts of operations, such as simple blits. In particular, this significantly speeds up XA by avoiding to pull the entire dest pixmap into GMEM, render tiles, and write it all back out again. This should also speed up resource copy-region and blit. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add a3xx supportRob Clark2013-06-0835-3/+8955
| | | | | | | | | | | | | | | | | | | | The adreno a3xx GPU is found in newer snapdragon devices, such as the nexus4. The a3xx is GLESv3 and OpenCL capable, although that is not enabled yet in gallium. Compared to a2xx, it introduces an entirely new unified shader ISA, and re-shuffles all or nearly all of the registers. The good news is that (for the most part) the registers are more orthogonal, not combining unrelated state in a single register. And that there is a lot more flexibility, so we don't need to patch and re-emit the shader like we did on a2xx. The shader compiler is currently quite dumb, there would be a lot of room for improvement with an optimizing pass. Despite that, with the a320 in my nexus4 it seems to be ~2-3x faster compared to the a220 in my HP touchpad. Signed-off-by: Rob Clark <[email protected]>
* freedreno: prepare for a3xxRob Clark2013-06-0849-2008/+2798
| | | | | | | | Split the parts that are specific to adreno a2xx series GPUs from the parts that will be in common with a3xx, so that a3xx support can be added more cleanly. Signed-off-by: Rob Clark <[email protected]>
* llvmpipe: move create_surface/destroy_surface functions to lp_surface.cRoland Scheidegger2013-06-072-59/+59
| | | | | | | Believe it or not but these two are actually the first two functions which really belong in this file nowadays. Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: add support for layered renderingRoland Scheidegger2013-06-0715-110/+195
| | | | | | | | | | | | | | | | Mostly just make sure the layer parameter gets passed through to the right places (and get clamped, can do this at setup time), fix up clears to clear all layers and disable opaque optimization. Luckily don't need to touch the jitted code. (Clears invoked via pipe's clear_render_target method will not work however since the pipe_util_clear function used for it doesn't handle clearing multiple layers yet.) v2: per Brian's suggestion, prettify var initialization and add some comments, add assertion for impossible layer specification for surface. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* ilo: fix textureSize() for single-layered array texturesChia-I Wu2013-06-081-2/+18
| | | | | We returned 0 instead of 1 for the number of layers when the array texutre is single-layered. This fixed it on GEN7+.
* tgsi: replace tgsi_file_names tgsi_file_names[] with tgsi_file_name() functionBrian Paul2013-06-072-4/+4
| | | | | | | | | This change came from the discovery that the STATIC_ASSERT to check that the number of register file strings didn't actually work. Similar changes could be made for the other string arrays in tgsi_string.c Reviewed-by: Jose Fonseca <[email protected]>
* ilo: advertise PIPE_CAP_CUBE_MAP_ARRAYChia-I Wu2013-06-071-2/+1
| | | | | It was supported but not advertised. Also remove TODO tag for PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT, as it is not a TODO.
* ilo: add support for TEX2/TXB2/TXL2 in fsChia-I Wu2013-06-071-3/+3
| | | | They were already supported, just being rejected in the TGSI translator.
* ilo: use slab allocator for transfersChia-I Wu2013-06-074-28/+39
| | | | | Slab allocator is perfect for transfer. Improved OpenArena performance by 1% with several casual runs.
* ilo: clean up states upon context destroyChia-I Wu2013-06-071-0/+38
| | | | We need to unreference resources that we referenced.
* ilo: unmap cp bo before destroying itChia-I Wu2013-06-071-1/+6
| | | | | The BOs are mapped in their entire life times for the chipsets we support so do not forget to unmap it.
* ilo: enable bo reuseChia-I Wu2013-06-071-0/+2
| | | | This magical line of code must have got lost at some point in the history...
* ilo: construct 3DSTATE_SF in create_rasterizer_state()Chia-I Wu2013-06-077-164/+194
| | | | Add ilo_rasterizer_sf and initialize it in create_rasterizer_state().
* ilo: construct 3DSTATE_CLIP in create_rasterizer_state()Chia-I Wu2013-06-075-50/+86
| | | | Add ilo_rasterizer_clip and initialize it in create_rasterizer_state().
* ilo: use emit_SURFACE_STATE() for render targetsChia-I Wu2013-06-079-127/+52
| | | | | | Introduce ilo_surface_cso and initialize it in create_surface(). With the change, we can emit SURFACE_STATE directly from the CSO and remove emit_surf_SURFACE_STATE(). We do not deal with depth/stencil surfaces yet.
* ilo: use emit_SURFACE_STATE() for constant buffersChia-I Wu2013-06-079-70/+26
| | | | | | Introduce ilo_cbuf_cso and initialize it in set_constant_buffer(). As ilo_view_surface is embedded in ilo_cbuf_cso, switch to emit_SURFACE_STATE() for constant buffers and remove emit_cbuf_SURFACE_STATE().
* ilo: add emit_SURFACE_STATE() for sampler viewsChia-I Wu2013-06-0710-99/+69
| | | | | | Introduce ilo_view_cso and initialize it in create_sampler_view(). Add emit_SURFACE_STATE() to GPE, which can emit SURFACE_STATE from ilo_view_surface.
* ilo: add ilo_view_surface for SURFACE_STATEChia-I Wu2013-06-073-125/+268
| | | | Define struct ilo_view_surface for SURFACE_STATE construction and emission.
* ilo: convert generic depth-stencil-alpha pipe state to ilo pipe stateCourtney Goeltzenleuchter2013-06-076-21/+51
| | | | | | | | | Moving the work to create time reduces the work at emit time. Saves time overall as create work is only done once. Fix compiler warning in gen7_pipeline_sol. [olv: remember pipe_alpha_state instead of pipe_depth_stencil_alpha_state in ilo_dsa_state]
* ilo: introduce vertex element CSOChia-I Wu2013-06-076-119/+227
| | | | | | | Introduce ilo_ve_cso and initialize it in create_vertex_elements_state(). This commit goes a step further by setting up mappings from HW VB to PIPE VB, which we failed to do previously. That allows us to support instanced rendering.
* ilo: simplify emit_3DSTATE_DEPTH_BUFFER()Chia-I Wu2013-06-076-63/+19
| | | | | | Remove hiz and dsa from the parameters. We would know whether HiZ buffer exists from ilo_texture once it is supported. DSA state should not affect 3DSTATE_DEPTH_BUFFER.