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* softpipe: silence some MSVC float/double warningsBrian Paul2013-03-211-6/+6
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* rbug: silence some MSVC signed/unsigned warningsBrian Paul2013-03-212-2/+2
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* radeonsi: Emit pixel shader state even when only the vertex shader changedMichel Dänzer2013-03-211-0/+5
| | | | | | | | Fixes random failures with piglit glsl-max-varyings. NOTE: This is a candidate for the 9.1 branch. Reviewed-by: Christian König <[email protected]>
* nvc0: fix max varying count, move CLIPVERTEX,FOG out of the wayChristoph Bumiller2013-03-203-12/+36
| | | | | | The card spews an error if I use all 128 generic slots. Apparently the real limit isn't just dictated by the address space layout.
* gallium: add TGSI_SEMANTIC_TEXCOORD,PCOORD v3Christoph Bumiller2013-03-2016-59/+52
| | | | | | | | | | | | | | | This makes it possible to identify gl_TexCoord and gl_PointCoord for drivers where sprite coordinate replacement is restricted. The new PIPE_CAP_TGSI_TEXCOORD decides whether these varyings should be hidden behind the GENERIC semantic or not. With this patch only nvc0 and nv30 will request that they be used. v2: introduce a CAP so other drivers don't have to bother with the new semantic v3: adapt to introduction gl_varying_slot enum
* r600g: don't emit SQ_DYN_GPR_RESOURCE_LIMIT_1 on caymanAlex Deucher2013-03-191-1/+0
| | | | | | | | | Doesn't exist on the asic and will cause a CS rejection if VM is disabled. Note: this is a candidate for the 9.1 branch. Signed-off-by: Alex Deucher <[email protected]>
* r600g: emit DB_SRESULTS_COMPARE_STATE0 on r6xx/r7xxAlex Deucher2013-03-192-1/+3
| | | | | | Not using HiS yet, but matches what we do on evergreen+. Signed-off-by: Alex Deucher <[email protected]>
* radeon/llvm: Do not link against libgallium when building statically.Maarten Lankhorst2013-03-191-1/+4
| | | | | | | NOTE: This is a candidate for the 9.1 branch. Tested-by: Vincent Lejeune <[email protected]> Signed-off-by: Maarten Lankhorst <[email protected]>
* freedreno: clear fixesRob Clark2013-03-192-5/+16
| | | | | | Some fixes for clearing only depth or only stencil. Signed-off-by: Rob Clark <[email protected]>
* radeonsi: enable indirect adressingChristian König2013-03-192-6/+1
| | | | | | | Fixing 16 piglit tests. Signed-off-by: Christian König <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: implement indirect adressing of constantsChristian König2013-03-191-6/+8
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: switch to using resource destribtors for constants v2Christian König2013-03-192-29/+37
| | | | | | | v2: remove superfluous mask, use buffer_size instead of constant Signed-off-by: Christian König <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: rework input fetch and output storeChristian König2013-03-192-122/+151
| | | | | | | Cleanup the code and implement indirect addressing. Signed-off-by: Christian König <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* tgsi: use separate structure for indirect address v2Christian König2013-03-194-6/+12
| | | | | | | | | | | | | | To further improve the optimization of source and destination indirect addressing we need the ability to store a reference to the declaration of the addressed operands. Since most of the fields in tgsi_src_register doesn't apply for an indirect addressing operand replace it with a separate tgsi_ind_register structure and so make room for extra information. v2: rename Declaration to ArrayID, put the ArrayID into () instead of [] Signed-off-by: Christian König <[email protected]>
* tgsi: remove TGSI_FILE_(IMMEDIATE|TEMP)_ARRAYChristian König2013-03-191-80/+0
| | | | | | Nobody seems to be using it, and only nv50 had a partial implementation. Signed-off-by: Christian König <[email protected]>
* radeon/llvm: Link against libgallium.la to fix an undefined symbolAndreas Boll2013-03-191-0/+1
| | | | | | | | | | | | | Ported from downstream: http://anonscm.debian.org/gitweb/?p=pkg-xorg/lib/mesa.git;a=blob;f=debian/patches/119-libllvmradeon-link.patch;h=ee47f8a07dbf33c32f8b57faed923680ed6648fb;hb=refs/heads/ubuntu%2B1 Fixes a regression introduced with f70c3853513637fa6ed38e75f73d472a9fa61213 NOTE: This is a candidate for the 9.1 branch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62434 Signed-off-by: Maarten Lankhorst <[email protected]>
* r600g: properly set non_disp tiling mode for DMA (v2)Alex Deucher2013-03-171-2/+6
| | | | | | | | | Needs to be set for depth, stencil, and fmask just like other blocks. v2: drop additional cayman bits for now Signed-off-by: Alex Deucher <[email protected]>
* r600g: Use blitter rather than DMA for 128bpp on cayman (v3)Alex Deucher2013-03-171-0/+11
| | | | | | | | | | | | | | | | | | | | | On cayman, 128bpp surfaces require non_disp ordering for hw access to both linear and tiled surfaces. When we use the 3D engine we can set the non_disp ordering on both the tiled and linear sides (via CB or texture), but when we use the DMA engine, we can only set the non_disp ordering on the tiled side, so after a L2T operation with the DMA engine, the data ends up in the wrong order on the tiled side. v2: cayman/TN only v3: fix comments Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=60802 Note: this is a candidate for the 9.1 branch. Signed-off-by: Alex Deucher <[email protected]>
* gallium/build: Fix visibility CFLAGS in automakeMaarten Lankhorst2013-03-163-1/+5
| | | | | | | | | | | v2: Andreas Boll <[email protected]> - Fix formatting - use one CFLAG per line NOTE: This is a candidate for the 9.1 branch. Signed-off-by: Maarten Lankhorst <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59238 Reviewed-by: Andreas Boll <[email protected]>
* softpipe: fix up NUM_ENTRIES confusionBrian Paul2013-03-143-13/+13
| | | | | | | | | | | | | | | | | | There were two different NUM_ENTRIES #defines for the framebuffer tile cache and the texture tile cache. Rename the later to fix the warnings: In file included from sp_flush.c:40:0: sp_tex_tile_cache.h:76:0: warning: "NUM_ENTRIES" redefined sp_tile_cache.h:78:0: note: this is the location of the previous definition In file included from sp_context.c:50:0: sp_tex_tile_cache.h:76:0: warning: "NUM_ENTRIES" redefined sp_tile_cache.h:78:0: note: this is the location of the previous definition Also, replace occurances of NUM_ENTRIES with Element() macro to be safer. Reviewed-by: José Fonseca <[email protected]>
* softpipe: Shrink context size.José Fonseca2013-03-141-1/+1
| | | | | | | | | | | | | | - each softpipe_tex_tile_cache 50*64*64*4*4 = 3,276,800 bytes - each softpipe_context has 3*32 softpipe_tex_tile_cache, i.e, each softpipe context is 314,572,800 bytes, i.e, 300MB That is, in a 32bits process (around 3GB virtual memory max), we can only fit 10 contexts. This change is a short-term hack to shrink the context size. Longer term we'll need to change how the texture cache works. Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: don't assert when trying to render to surfaces with multiple layersRoland Scheidegger2013-03-142-2/+3
| | | | | | | instead just warn when creating the surface, rendering will simply happen to first layer. Reviewed-by: Jose Fonseca <[email protected]>
* softpipe: don't assert when creating surfaces with multiple layersRoland Scheidegger2013-03-142-16/+32
| | | | | | | | | | | | We can't handle them yet, however we can safely just warn (we will just render to first layer, which is fine since we can't handle rendertarget system value neither). Also make behavior more predictable with buffer surfaces (it would sometimes hit bogus asserts because of the union in the surface, instead create the surface but assert when trying to set a buffer in the framebuffer). Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: Fix geometry shader token leak.José Fonseca2013-03-131-0/+1
| | | | Trivial. Matches softpipe's code.
* radeon/llvm: Add missing license headersTom Stellard2013-03-132-0/+52
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Make radeon_llvm_util.cpp a C fileTom Stellard2013-03-133-29/+8
| | | | All the functions in this file are now implemented in C.
* radeon/llvm: Optimize radeon_llvm_strip_unused_kernels()Tom Stellard2013-03-132-17/+10
| | | | | | | | Just delete unused kernels rather than marking them as internal and running the GlobalDCE pass. Also implement this function in C and inline it into radeon_llvm_get_kernel_module()
* radeon/llvm: Implement radeon_llvm_get_kernel_module() using the C APITom Stellard2013-03-132-7/+15
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* radeon/llvm: Implement radeon_llvm_get_num_kernels() using the C APITom Stellard2013-03-131-6/+1
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* radeon/llvm: Implement radeon_llvm_parse_bitcode() using C APITom Stellard2013-03-132-8/+11
| | | | Also make the function static since it is not used anywhere else.
* r600g/llvm: Move llvm wrapper functions into the radeon directoryTom Stellard2013-03-137-38/+35
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* autotools: Add missing top-level include dir.José Fonseca2013-03-131-0/+1
| | | | | Fixes autotools build failure. Not sure if there are more, as I have difficulties in building the full tree.
* mesa: Use PACKAGE_BUGREPORT macro.Matt Turner2013-03-121-1/+1
| | | | Reviewed-by: Eric Anholt <[email protected]>
* radeonsi: Fix off-by-one for maximum vertex element index in some casesMichel Dänzer2013-03-121-2/+8
| | | | | | | | | | | In cases where the vertex element size is smaller than the vertex buffer stride, the previous calculation could end up 1 too low. This would result in the GPU using index 0 instead of the maximum index for those elements, which would be visible as intermittent distorted triangles. NOTE: This is a candidate for the 9.1 branch. Reviewed-by: Alex Deucher <[email protected]>
* nvc0: avoid crash on updating RASTERIZE_ENABLE stateChristoph Bumiller2013-03-122-4/+18
| | | | | When doing a blit with the 3D engine, the rasterizer or zsa cso may be NULL.
* nvc0: add MP trap handler for nve4Christoph Bumiller2013-03-124-15/+314
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* nvc0: they removed the NTID,NCTAID,GRIDID registers on nve4Christoph Bumiller2013-03-126-23/+66
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* nvc0: implement compute support for nve4Christoph Bumiller2013-03-1218-78/+1882
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* nvc0/ir: try to fix CAS (CompareAndSwap)Christoph Bumiller2013-03-122-1/+42
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* nv50/ir: add CCTL (cache control) opChristoph Bumiller2013-03-125-4/+33
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* nvc0/ir/emit: fix emission of large address offsetsChristoph Bumiller2013-03-121-8/+50
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* nvc0: add SHADER/COMPUTE_RESOURCE bind flags to format tableChristoph Bumiller2013-03-121-43/+53
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* nouveau: align PIPE_BIND_SHADER,COMPUTE_RESOURCEs to 256 bytesChristoph Bumiller2013-03-121-1/+3
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* nv50,nvc0: copy writable flag on surface creationChristoph Bumiller2013-03-122-0/+2
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* nv50/ir: add support for different sampler and resource index on nve4Christoph Bumiller2013-03-123-37/+51
| | | | | | | | | | And remove non-working code for indirect sampler/resource selection. Will be added back later. Includes code from "nv50/ir/tgsi: Resource indirect indexing" by Francisco Jerez (when mixing the R and S handles we can only specify them via a register, i.e. indirectly, unless we upload all the used handle combinations to c[] space, which we don't for now).
* nv50/ir: implement splitting of 64 bit ops after RAChristoph Bumiller2013-03-126-39/+98
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* nvc0/ir: skip back edges when determining latest sched valueChristoph Bumiller2013-03-121-3/+4
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* nvc0/ir: use large issue delay after RET, tooChristoph Bumiller2013-03-121-1/+1
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* nv50/ir: fix size adjustment for sched info for multiple functionsChristoph Bumiller2013-03-121-6/+11
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* nv50/ir: print function inputs and outputsChristoph Bumiller2013-03-121-1/+22
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