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* llvmpipe: increase number of subpixel bits to eightZack Rusin2013-09-233-11/+17
| | | | | | | | | | | | | Unfortunately d3d10 requires a lot higher precision (e.g. wgf11clipping tests for it). The smallest number of precision bits with which it passes is 8. That means that we need to decrease the maximum length of an edge that we can handle without subdivision by 4 bits. Abstracted the code a bit to make it easier to change once to switch to 64bit rasterization. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: José Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeon/uvd: async flush the UVD csChristian König2013-09-221-1/+1
| | | | | | | No need to block for the CS thread here. Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: fast color clears for single-sample buffersGrigori Goronzy2013-09-205-11/+86
| | | | | | | | | | | Allocate a CMASK on demand and use it to fast clear single-sample colorbuffers. Both FBOs and window system colorbuffers are fast cleared. Expand as needed when colorbuffers are mapped or displayed on screen. v2: cosmetics, move transfer expansion into dma_blit Signed-off-by: Marek Olšák <[email protected]>
* r600g: add support for separately allocated CMASKsGrigori Goronzy2013-09-204-10/+60
| | | | | | v2: check for NULL cbufs Signed-off-by: Marek Olšák <[email protected]>
* gallium: add flush_resource context functionMarek Olšák2013-09-2019-0/+151
| | | | | | | | | r600g needs explicit flushing before DRI2 buffers are presented on the screen. v2: add (stub) implementations for all drivers, fix frontbuffer flushing v3: fix galahad Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: simplify and fix MSAA texture sampling for array texturesMarek Olšák2013-09-202-27/+17
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix textureOffset and texelFetchOffset GLSL functionsMarek Olšák2013-09-201-9/+23
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* llvmpipe: Fix rendering to PIPE_FORMAT_R10G10B10A2_UNORM.José Fonseca2013-09-201-6/+78
| | | | | | | We must take rounding in consideration when re-scaling to narrow normalized channels, such as 2-bit normalized alpha. Reviewed-by: Roland Scheidegger <[email protected]>
* freedreno/a3xx: fix typo mixup w/ mipfilterRob Clark2013-09-191-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix glReadPixelsRob Clark2013-09-191-2/+2
| | | | | | | duh, we still need to flush if there are pending draws and it isn't an unsynchronized case. Signed-off-by: Rob Clark <[email protected]>
* ilo: make ilo_bind_sampler_states return voidChia-I Wu2013-09-171-16/+25
| | | | | So that it can be hooked up pipe_context::bind_sampler_states that is currently living on another branch.
* nouveau: fix regression since float comparison instructions (v2)Dave Airlie2013-09-166-14/+14
| | | | | | | | | | Fix the return type and allow src and dst types for comparison to be separate, this at least fixes the two test cases I've written. v2: drop the u32->s32 change Acked-by: Christoph Bumiller <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* freedreno: PIPE_TRANSFER_DISCARD_WHOLE_RESOURCERob Clark2013-09-141-17/+43
| | | | | | | When the old contents do not need to be preserved, it is faster to create a new backing bo rather than stall. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix VFD_INDEX_MAX overflowRob Clark2013-09-141-1/+1
| | | | | | | max_index may be 0xffffffff. The hardware does not need 1 + max_index (although it does not hurt unless max_index wraps around to zero). Signed-off-by: Rob Clark <[email protected]>
* freedreno: add debug option to disable GMEM bypassRob Clark2013-09-143-1/+3
| | | | | | Useful for debugging. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: handle front_ccwRob Clark2013-09-145-17/+14
| | | | | | Used by supertuxkart. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: stencil fixesRob Clark2013-09-149-7/+30
| | | | | | | | For mem->gmem we don't sample depth/stencil as it's native type. So we need to setup the swizzle state for the sampler based on the format used for sampling. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: alpha-testRob Clark2013-09-147-7/+29
| | | | | | | Needed by some games, like etuxracer and supertuxkart which use alpha test rather than blending, to handle texture transparency. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: implement SUBRob Clark2013-09-141-3/+11
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: use INDIRECT state load for shadersRob Clark2013-09-143-8/+29
| | | | | | | | | With a debug option to force DIRECT (mainly to make it easier for capturing cmdstream dumps). Using INDIRECT for large shaders at least makes a noticable reduction in CPU load, which helps for CPU limited games. Signed-off-by: Rob Clark <[email protected]>
* freedreno: avoid stalling at ringbuffer wraparoundRob Clark2013-09-142-22/+41
| | | | | | | | | Because of how the tiling works, we can't really flush at arbitrary points very easily. So wraparound is handled by resetting to top of ringbuffer. Previously this would stall until current rendering is complete. Instead cycle through multiple ringbuffers to avoid a stall. Signed-off-by: Rob Clark <[email protected]>
* freedreno: emit markers to scratch registersRob Clark2013-09-144-0/+33
| | | | | | | | | Emit markers by writing to scratch registers in order to "triangulate" gpu lockup position from post-mortem register dump. By comparing register values in post-mortem dump to command-stream, it is possible to narrow down which DRAW_INDX caused the lockup. Signed-off-by: Rob Clark <[email protected]>
* freedreno: split out WFI helperRob Clark2013-09-145-10/+12
| | | | | | Mostly just to give an easy debug/instrumentation point. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fd_draw helperRob Clark2013-09-146-52/+55
| | | | | | | Have a single helper that all draws come through.. mainly for a convenient debug and instrumentation point. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix gpu lockup in some piglit testsRob Clark2013-09-141-1/+1
| | | | | | | | | The varying-out config comes from the inputs of the frag shader (so that we aren't exporting unneeded varyinges). The varyings-count should come from the frag shader as well, to avoid a discrepency in configuration and resulting gpu lockup. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: add LITRob Clark2013-09-141-3/+142
| | | | | | Needed by glxgears and etuxracer ;-) Signed-off-by: Rob Clark <[email protected]>
* freedreno: multi-slice resources (cubemap, mipmap, etc)Rob Clark2013-09-1415-52/+141
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeonsi: fix and enable transform feedback for CIKMarek Olšák2013-09-134-28/+40
| | | | | | The CP_STRMOUT_CNTL register was moved again. Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: fix gl_InstanceID with non-zero start_instanceMarek Olšák2013-09-131-3/+4
| | | | | | | | start_instance doesn't affect gl_InstanceID. There's no piglit test, but it's kinda obvious the code was wrong. Reviewed-by: Christian König <[email protected]>
* radeonsi: enable streamout AKA transform feedback for SIMarek Olšák2013-09-131-10/+4
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement streamout shader supportMarek Olšák2013-09-133-15/+276
| | | | | | | | | | | The shader is responsible for writing to streamout buffers using the TBUFFER_STORE_FORMAT_* instructions. The locations of some input SGPRs and VGPRs are assigned dynamically, because the input SGPRs controlling streamout are not declared if they are not needed, decreasing the indices of all following inputs. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement glDrawTransformFeedback functionalityMarek Olšák2013-09-133-0/+30
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix streamout queriesMarek Olšák2013-09-131-4/+5
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement streamout flush properlyMarek Olšák2013-09-131-1/+7
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: bind streamout buffers to VGT and the vertex shaderMarek Olšák2013-09-134-8/+81
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: handle rasterizer_discard and set GS_OUT_PRIM_TYPEMarek Olšák2013-09-133-1/+31
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: initialize the first CS like any otherMarek Olšák2013-09-135-5/+15
| | | | | | | | | So that the "init" state is always emitted first and not later in draw_vbo. This fixes streamout where the "init" state, which disables streamout, was emitted in draw_vbo after streamout was enabled. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: integrate shared streamout stateMarek Olšák2013-09-137-38/+20
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon: don't emit streamout state if there are no streamout buffersMarek Olšák2013-09-131-0/+2
| | | | | | | This could happen if set_stream_output_targets is called twice in a row without a draw call in between. Reviewed-by: Michel Dänzer <[email protected]>
* radeon: don't emit VGT_STRMOUT_BUFFER_BASE on SIMarek Olšák2013-09-131-31/+54
| | | | | | The register doesn't exist on SI. Reviewed-by: Michel Dänzer <[email protected]>
* radeon/uvd: move more logic into the common filesChristian König2013-09-126-40/+23
| | | | | | | | Move the code back into the common UVD files since we now have base structures for R600 and radeonsi. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/uvd: use more sane defaults for bitstream buffer sizeChristian König2013-09-121-1/+3
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* trace: Support bigger TGSI shaders.José Fonseca2013-09-121-1/+1
| | | | Trivial.
* Move nv30, nv50 and nvc0 to nouveau.Johannes Obermayr2013-09-11160-638/+430
| | | | | | | | | | | | | | | | It is planned to ship openSUSE 13.1 with -shared libs. nouveau.la, nv30.la, nv50.la and nvc0.la are currently LIBADDs in all nouveau related targets. This change makes it possible to easily build one shared libnouveau.so which is then LIBADDed. Also dlopen will be faster for one library instead of three and build time on -jX will be reduced. Whitespace fixes were requested by 'git am'. Signed-off-by: Johannes Obermayr <[email protected]> Acked-by: Christoph Bumiller <[email protected]> Acked-by: Ian Romanick <[email protected]>
* radeonsi: Add parentheses around '|' operands.Vinson Lee2013-09-101-1/+1
| | | | | | | | | | | | | | Fixes GCC parentheses warning. r600_texture.c: In function 'si_texture_create': r600_texture.c:518:20: warning: suggest parentheses around arithmetic in operand of '|' [-Wparentheses] !(templ->bind & PIPE_BIND_CURSOR | PIPE_BIND_LINEAR)) { ^ Fixes "Wrong operator used" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ilo: preliminary GEN 7.5 supportChia-I Wu2013-09-0810-107/+236
| | | | | This is based on grepping for brw->is_haswell in i965 to see how GEN 7.5 differs from GEN 7. Slightly tested with Xonotic and some Mesa demos.
* r600g: remove DMA paddingAlex Deucher2013-09-061-9/+0
| | | | | | | This is now handled in the winsys. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* gallium, intel: Implements new __DRI_IMAGE_USE_LINEAR and PIPE_BIND_LINEAR ↵Axel Davy2013-09-067-6/+17
| | | | | | flags to enforce no tiling. Signed-off-by: Axel Davy <[email protected]>
* i915g: Document fall-through switchStéphane Marchesin2013-09-061-4/+3
| | | | Fixes warning reported by Coverity.
* i915g: Handle i915->batch == NULL correctly in flushStéphane Marchesin2013-09-061-1/+4
| | | | Fixes warning reported by Coverity.
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