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* radeonsi: remove si_llvm_add_attributeMarek Olšák2018-03-073-25/+16
* radeonsi: fix passing address32_hi to LLVM for high valuesMarek Olšák2018-03-071-2/+5
* radeonsi: assume has_virtual_memory == trueMarek Olšák2018-03-072-34/+18
* radeonsi: add/update assertions for 32-bit address spaceMarek Olšák2018-03-072-3/+18
* radeonsi: prevent a negative buffer offset in si_upload_descriptorsMarek Olšák2018-03-071-4/+3
* radeonsi: properly extract a buffer address from a descriptorMarek Olšák2018-03-071-1/+7
* radeonsi: fix vertex buffer address computation with full 64-bit addressesMarek Olšák2018-03-071-3/+3
* radeonsi: mask out high VM address bits in registers where neededMarek Olšák2018-03-073-22/+24
* ac: add ac_count_scratch_private_memory()Samuel Pitoiset2018-03-061-28/+4
* tgsi/scan: use wrap-around shift behavior explicitly for file_maskRoland Scheidegger2018-03-062-2/+7
* radeonsi/nir: fix handling of doubles for gs inputsTimothy Arceri2018-03-061-2/+6
* radeonsi: move si_nir_load_input_gs() to si_shader.cTimothy Arceri2018-03-063-29/+20
* broadcom/vc4: Add support for HW perfmonBoris Brezillon2018-03-055-12/+249
* r600: fix color export maskRoland Scheidegger2018-03-051-0/+1
* freedreno/ir3: start dealing with half-precisionRob Clark2018-03-053-30/+81
* freedreno/ir3: fix fixing-up register footprintRob Clark2018-03-052-18/+27
* freedreno: surfaces can be PIPE_BUFFERRob Clark2018-03-051-4/+10
* freedreno/a5xx: handle compute resourcesRob Clark2018-03-051-2/+4
* freedreno/ir3: ignore return jumpRob Clark2018-03-051-0/+1
* freedreno: add some more compute capsRob Clark2018-03-052-4/+21
* freedreno/a5xx: don't expose 64b pointers yetRob Clark2018-03-051-2/+5
* freedreno: steal handy macro for compute caps from nouveauRob Clark2018-03-051-42/+17
* freedreno: add global_bindings stateRob Clark2018-03-054-4/+85
* freedreno/ir3: small cleanupRob Clark2018-03-051-3/+3
* freedreno: add pctx->memory_barrier()Rob Clark2018-03-051-0/+8
* freedreno/ir3: cmdline compiler updates for spv shadersRob Clark2018-03-051-0/+7
* ac: add ac_build_fsign()Samuel Pitoiset2018-03-051-11/+4
* ac: add ac_build_isign()Samuel Pitoiset2018-03-051-8/+2
* ac: add ac_build_fract()Samuel Pitoiset2018-03-051-8/+5
* virgl: add offset alignment values to to v2 caps struct[email protected]2018-03-053-2/+6
* virgl: reduce some default capset limits.Dave Airlie2018-03-051-8/+8
* virgl: handle getting new capsets.Dave Airlie2018-03-051-1/+24
* radeonsi/nir: call ac_lower_indirect_derefs()Timothy Arceri2018-03-054-4/+6
* radeonsi: add chip class to compiler_ctx_stateTimothy Arceri2018-03-053-0/+4
* swr/rast: Fix macOS macro.Vinson Lee2018-03-041-2/+2
* svga: add SVGA_NEW_PRESCALE to the tracked dirty mask for gsCharmaine Lee2018-03-021-1/+2
* svga: fix blending regressionBrian Paul2018-03-021-11/+24
* svga: check svga_have_vgpu10() in svga_delete_blend_state()Brian Paul2018-03-021-1/+1
* svga: if svga_update_state() fails, skip the draw callBrian Paul2018-03-021-5/+5
* svga: let svga_update_state_retry() return a boolBrian Paul2018-03-022-6/+9
* svga: s/unsigned/boolean/ for a few local varsBrian Paul2018-03-021-6/+6
* radeonsi: fix radeon create encoder returnBoyuan Zhang2018-03-021-1/+1
* r600/cayman: fix fragcood loading recip generation.Dave Airlie2018-03-021-1/+1
* radeonsi/nir: increase values to 8 for gs fetch.Dave Airlie2018-03-011-1/+1
* radeonsi: set some context vars for nir pathTimothy Arceri2018-03-011-6/+10
* broadcom/vc5: Fix regression in the page-cache slice size alignment.Eric Anholt2018-02-281-3/+6
* r600/shader: when using images always load thread id gpr at start (v2)Dave Airlie2018-02-281-15/+7
* r600: fix whitespace in recent 1d texture commit.Dave Airlie2018-02-281-1/+1
* swr/rast: revert clip distance precisionGeorge Kyriazis2018-02-282-4/+17
* swr/rast: Faster frustum prim cullingGeorge Kyriazis2018-02-281-3/+7
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