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* ilo: switch to ilo states for VF stageChia-I Wu2013-06-077-53/+55
| | | | | | | | | | Define and use struct ilo_vb_state; struct ilo_ve_state; struct ilo_ib_state; in ilo_context.
* ilo: move hardware limits to ilo_gpe.hChia-I Wu2013-06-072-22/+56
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* llvmpipe: bump 3d and cube map limits to 2048 and 8192 respectivelyRoland Scheidegger2013-06-061-2/+2
| | | | | | | These should just work, required by d3d10. Too large resources will get thrown out separately anyway. Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: improve alignment calculation for fetching/storing pixelsRoland Scheidegger2013-06-051-12/+21
| | | | | | | | | | | | | | | | This was always doing per-pixel alignment which isn't necessary, except for the buffer case (due to the per-element offset). The disabled code for calculating it was incorrect because it assumed that always the full block would be fetched, which may not be the case, so fix this up. The original code failed for instance for r10g10b10a2 the alignment would have been calculated as 4 (block_width) * 4 (bytes) so 16, but the actual fetch may have only fetched 2 values at a time, hence only alignment 8 - it is unclear what exactly would happen in this case (alignment larger than size to fetch). So just use the (already calculated) fetch size instead and get alignment from that which should always work, no matter if fetching 1,2 or 4 pixels. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: reduce alignment requirement for 1d resources from 4x4 to 4x1Roland Scheidegger2013-06-059-44/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For rendering to buffers, we cannot have any y alignment. So make sure that tile clear commands only clear up to the fb width/height, not more (do this for all resources actually as clearing more seems pointless for other resources too). For the jit fs function, skip execution of the lower half of the fragment shader for the 4x4 stamp completely, for depth/stencil only load/store the values from the first row (replace other row with undef). For the blend function, also only load half the values from fs output, replace the rest with undefs so that everything still operates on the full 4x4 block to keep code the same between 4x1 and 4x4 (except for load/store of course which also needs to skip (store) or replace these values with undefs (load))., at the cost of slightly less optimal code being produced in some cases. Also reduce 1d and 1d array alignment too, because they can be handled the same as buffers so don't need to waste memory. v2: don't try to run special blend code for 4x1, (very) slightly less complexity if we just use the same code as for 4x4 which may or may not make it easier to optimize in the future (as we care a lot more about 4x4 performance than 1d). v2: don't use undef values for unused fs src outputs with llvm 3.1 as it apparently can trigger a bug in llvm. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: cleanup of generate_unswizzled_blendRoland Scheidegger2013-06-051-22/+37
| | | | | | | | | | | | | Some parameters were used inconsistently, for instance not using block_width/block_height/block_size for deferring number of pixels but rather relying on guesses from the number of fragment shaders etc, so fix this up (no actual change in behavior since the block size stays fixed). (Though most of the code would work with different block_height, with three exceptions, one being the hacked r11g11b10 conversions and twiddle code which only work with block_height 2 not 1, and the last one being blend vector type not being 128bit wide.) Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: enhance special sse2 4x4f and 2x8f -> 1x16ub conversionRoland Scheidegger2013-06-051-0/+2
| | | | | | | | | | | | | There's no good reason why it can't handle 2x4f->1x8ub, 1x4f->1x4ub and 1x8f->1x8ub cases, there might be legitimate reasons why we don't have enough input vectors for a full destination vector, and using pack intrinsics should still be much better than using generic conversion (it looks like convert_alpha from the blend code might hit this though I suspect it could be avoided). v2: add another test vector format to lp_test_conv so this gets tested. Reviewed-by: Jose Fonseca <[email protected]>
* softpipe: draw_find_shader_output returns -1 on invalid outputsZack Rusin2013-05-301-1/+1
| | | | | | | | It was changed from 0 to allow shader outputs at 0 that are different from position. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radeonsi/compute: Upload work group, work item size in input bufferTom Stellard2013-06-031-11/+27
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* radeonsi/compute: Pass kernel arguments in a buffer v2Tom Stellard2013-06-033-35/+44
| | | | | v2: - Fix memory leak in si_set_constant_buffer()
* radeonsi/compute: Implement un-binding of global buffersTom Stellard2013-06-031-12/+19
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* radeonsi/compute: Support multiple kernels in a compute programTom Stellard2013-06-031-9/+18
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* radeonsi/compute: Add missing PIPE_COMPUTE capsTom Stellard2013-06-031-0/+16
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* llvmpipe: fix bogus assertions for buffer surfacesRoland Scheidegger2013-06-011-2/+2
| | | | | | | | | | One of the assertion made no sense for buffer rendertargets (due to the union), so drop it. (The same assertion is present already in the path for texture surfaces later.). v2: make assertion completely accurate (suggested by Jose). Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: reduce alignment requirement for resources from 64x64 to 4x4Roland Scheidegger2013-05-317-53/+83
| | | | | | | | | | | | | | | | | | | | | | | | The overallocation was very bad especially for things like 1d array textures which got blown up by a factor of 64. (Even ordinary smallish 2d textures benefit a lot from this, a mipmapped 64x64 rgba8 texture previously used 7*16kB = 112kB instead of now ~22kB.) 4x4 is chosen because this is the size the jit functions run on, so making it smaller is going to be a bit more complicated. It is actually not strictly 4x4 pixel, since we'd want to avoid situations where different threads are rendering to the same cacheline so we keep cacheline size alignment in x direction (often 64bytes). To make this work introduce new task width/height parameters and make sure clears don't clear the whole tile if it's a partial tile. Likewise, the rasterizer may produce fragments outside the 4x4 blocks present in a tile, so don't call the jit function for them. This does not yet fix rendering to buffers (which cannot have any y alignment at all), and 1d/1d array textures are still overallocated by a factor of 4. v2: replace magic number 4 with LP_RASTER_BLOCK_SIZE, fix size of buffers allocated (needed in case we render to them). Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: Remove x/y from cmd_binAdam Jackson2013-05-316-47/+30
| | | | | | | | | | These were mostly just a waste of memory and cache pressure, and were really only used for debugging. This change reduces instruction count (as measured by callgrind's Ir event) of gnome-shell-perf-tool on Ivybridge by 3.5% ± 0.015% (n=20). Signed-off-by: Adam Jackson <[email protected]>
* r600g/sb: fix broken assertVadim Girlin2013-05-311-1/+1
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* ilo: simplify shader variant handlingCourtney Goeltzenleuchter2013-05-302-25/+2
| | | | | | Remove hash function on shader variants. Nature of variants limits them to a small number and thus its more efficient to just do a memory compare of the actual shader structures rather than compute and compare hashes.
* svga: add PIPE_CAP_MAX_VIEWPORTS to switch to silence warningBrian Paul2013-05-291-0/+2
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* llvmpipe: clamp scissors to be between 0 and maxZack Rusin2013-05-255-3/+13
| | | | | | | | | | We need to clamp to make sure invalid shader doesn't crash our driver. The spec says to return 0-th index for everything that's out of bounds. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: José Fonseca<[email protected]> Reviewed-by: Brian Paul <[email protected]>
* draw: fixup draw_find_shader_outputZack Rusin2013-05-252-5/+5
| | | | | | | | | | | | | | | | | draw_find_shader_output like most of the code in draw used to depend on position always being at output slot 0. which meant that any other attribute being at 0 could signify an error. unfortunately position can be at any of the output slots, thus other attributes can occupy slot 0 and we need to mark the ones which were not found by something else. This commit changes draw_find_shader_output so that it returns -1 if it can't find the given attribute and adjust the code that depended on it returning >0 whenever it correctly found an attrib. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: José Fonseca<[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: implement support for multiple viewportsZack Rusin2013-05-2511-36/+79
| | | | | | | | | | Largely related to making sure the rasterizer can correctly pick out the correct scissor box for the current viewport. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: José Fonseca<[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: Add support for multiple viewportsZack Rusin2013-05-2524-128/+205
| | | | | | | | | | | | Gallium supported only a single viewport/scissor combination. This commit changes the interface to allow us to add support for multiple viewports/scissors. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: José Fonseca<[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: get rid of tiled/linear layout remainsRoland Scheidegger2013-05-296-226/+47
| | | | | | | Eliminate the rest of the no longer needed layout logic. (It is possible some code could be simplified a bit further still.) Reviewed-by: Jose Fonseca <[email protected]>
* radeonsi: Enable GLSL 1.30Michel Dänzer2013-05-281-1/+1
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* radeonsi: Handle TGSI TXQ opcodeMichel Dänzer2013-05-282-3/+33
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* radeonsi: Add support for TGSI TXF opcodeMichel Dänzer2013-05-282-14/+51
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* radeonsi: Use tgsi_util_get_texture_coord_dim()Michel Dänzer2013-05-281-25/+7
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* radeonsi: Handle TGSI_SEMANTIC_CLIPDISTMichel Dänzer2013-05-281-4/+17
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* radeonsi: Make border colour state handling safe for integer texturesMichel Dänzer2013-05-282-20/+27
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* radeonsi: Fix hardware state for dual source blendingMichel Dänzer2013-05-284-6/+17
| | | | | Set up CB_SHADER_MASK register according to pixel shader exports, and enable some minimal state for colour buffer 1 in case dual source blending is used.
* r600g/sb: handle more cases for folding in gvn passVadim Girlin2013-05-282-28/+118
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: improve folding for SETccVadim Girlin2013-05-271-8/+98
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: optimize CNDcc instructionsVadim Girlin2013-05-273-1/+113
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: improve optimization of conditional instructionsVadim Girlin2013-05-276-21/+96
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* ilo: enable multiple constant buffersChia-I Wu2013-05-271-1/+1
| | | | This effectively enables uniform buffer object support.
* ilo: add support for indirect access of CONST in FSChia-I Wu2013-05-272-2/+99
| | | | | Unlike other register files, CONST is read with a message and indirect access is easier to implement.
* ilo: add support for TBOs on GEN6Chia-I Wu2013-05-271-8/+26
| | | | This hunk was missing in the last commit.
* ilo: advertise supports for pure integer formatsChia-I Wu2013-05-271-2/+3
| | | | For pure integer formats, no filtering nor blending is needed.
* ilo: add support for texture buffer objectsChia-I Wu2013-05-272-10/+32
| | | | | Take care of sampler views that have buffers as the underlying resources. Update caps related to TBOs.
* r600g/sb: improve handling of KILL instructionsVadim Girlin2013-05-273-89/+139
| | | | | | | This patch improves handling of unconditional KILL instructions inside the conditional blocks, uncovering more opportunities for if-conversion. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix peephole optimization for PRED_SETEVadim Girlin2013-05-271-1/+1
| | | | | | | Fixes incorrect condition that prevented optimization for PRED_SETE/PRED_SETE_INT. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix scheduling of PRED_SET instructionsVadim Girlin2013-05-272-2/+18
| | | | | | | | | | | | | | PRED_SET instructions that update exec mask should be scheduled immediately prior to the "if-then-else" block, because any instruction that is inserted after alu clause with PRED_SET and before conditional block is also conditionally executed by hw (exec mask is already updated at that moment). Propbably it's better to make PRED_SET a part of conditional "if-then-else" block in the IR to handle this more cleanly, but for now this temporary solution should prevent the problem. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix handling of preloaded inputs for compute shadersVadim Girlin2013-05-251-0/+4
| | | | | | | | | | For compute shaders we need to let the backend know that GPRs 0 and 1 are preloaded with some compute-specific input values, otherwise any use of these regs without previous definition is considered as undefined value and usually is simply replaced with 0. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix incorrect assertVadim Girlin2013-05-241-1/+1
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: relax some restrictions for FETCH instructionsVadim Girlin2013-05-241-9/+8
| | | | | | | | This allows GVN rewrite pass to propagate non-const (register) values to FETCH source operands, helping to eliminate unnecessary copies in some cases. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: relax register allocation for compute shadersVadim Girlin2013-05-242-2/+16
| | | | | | | | | | | | | | We have to assume that all GPRs in compute shader can be indirectly addressed because LLVM backend doesn't provide any indirect array info. That's why for compute shaders GPR array is created that covers all used GPRs (0..r600_bytecode::ngpr-1), but this seriously restricts register allocation in sb. This patch checks for actual use of indirect access in the shader and if it's not used then GPR array is not created, so that regalloc is not unnecessarily restricted. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix gpr array handling for compute shadersVadim Girlin2013-05-241-1/+1
| | | | | | Fixes segfault with bfgminer and R600_DEBUG=sbcl. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix buffer overflow in sb_ostreamVadim Girlin2013-05-241-1/+1
| | | | | | Fixes segfault during bytecode dump with bfgminer kernel Signed-off-by: Vadim Girlin <[email protected]>
* r600g/compute: Use common transfer_{map,unmap} functions for global resourcesTom Stellard2013-05-231-44/+24
| | | | Reviewed-by: Marek Olšák <[email protected]>
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