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* r600g: cleanup state function namesMarek Olšák2012-09-133-37/+37
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: consolidate initialization of common state functionsMarek Olšák2012-09-135-150/+81
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: simplify flushingMarek Olšák2012-09-1312-190/+210
| | | | | | | | | | | | Based on the patch called "simplify and fix flushing and synchronization" by Jerome Glisse. Rebased, removed unneded code, simplified more and cleaned up. Also, SH_ACTION_ENA is not set when changing shaders (hw doesn't seem to need it). It's only used to flush constant buffers. Reviewed-by: Jerome Glisse <[email protected]>
* radeon/llvm: Fix lowering of vbuildTom Stellard2012-09-137-93/+19
| | | | | | Some of the old AMDIL code was hard-coding subreg indices when creating the VBUILD node, which was making it difficult to match the vector_insert patterns.
* radeon/llvm: Support fmul on SITom Stellard2012-09-131-1/+4
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* radeonsi: Properly handle NULL sampler views.Michel Dänzer2012-09-121-3/+3
| | | | | | | | | | Fixes piglit shaders/glsl-fs-uniform-sampler-array and many other similar tests. In fact, I just completed a piglit quick-driver.tests run without any GPU lockups or even VM protection faults. Yay! Signed-off-by: Michel Dänzer <[email protected]>
* radeonsi: Fix calculation of number of records in buffer resource.Michel Dänzer2012-09-121-1/+1
| | | | | | | | | | | The value was too small by 1 in some cases (non-first of several vertex elements interleaved in a single buffer). Fixes intermittent incorrect geometry in many apps, e.g. piglit spec/EXT_texture_snorm/fbo-generatemipmap-formats. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/llvm: Fix operand order of V_CNDMASK in custom inserterTom Stellard2012-09-111-1/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Assert if we try to encode an unknown registerTom Stellard2012-09-111-1/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Add register encoding for VCCTom Stellard2012-09-111-0/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Ignore special registers when calculating reg countTom Stellard2012-09-111-0/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Handle position input parameter for pixel shaders v2Tom Stellard2012-09-114-1/+53
| | | | | | | | v2: - Don't increment ninterp or set any of the have_* flags for TGSI_SEMANTIC_POSITION Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Coding style fixesTom Stellard2012-09-114-31/+31
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Move interpolation mode check into the compilerTom Stellard2012-09-112-12/+21
| | | | | | | The compiler needs to know which interpolation modes are enabled, so it knows which values will be preloaded into the VGPRs. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Add missing interpolation mode to check for enabled modesTom Stellard2012-09-111-0/+1
| | | | | | | At least one interpolation mode must be enable, but the code that checks this was not checking for perspective center. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Pass shader type to the compilerTom Stellard2012-09-111-0/+12
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Add SHADER_TYPE instructionTom Stellard2012-09-118-1/+32
| | | | | | | This allows the program to specify the type of shader being compiled (e.g. PXEL, VERTEX, etc.) Reviewed-by: Michel Dänzer <[email protected]>
* r600g: avoid GPU doing constant preload from random addressJerome Glisse2012-09-112-0/+40
| | | | | | | | | Previous command stream might have set any of the constant buffer and the previous address might no longer be valid thus GPU might preload constant from random invalid address and possibly triggering lockup. Signed-off-by: Jerome Glisse <[email protected]>
* radeonsi: Texture border colour fixes.Michel Dänzer2012-09-113-8/+56
| | | | | | | | | | * Handle arbitrary border colours. * Use correct packing format for detecting special border colours. Fixes piglit tex-border-1 and probably many other tests using border colours. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Handle NULL sampler states.Michel Dänzer2012-09-111-1/+1
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: remove unused functionMarek Olšák2012-09-112-22/+0
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* r600g: fix printf warningMarek Olšák2012-09-111-1/+2
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* nvc0/ir: add initial code to support GK110 ISA encodingChristoph Bumiller2012-09-0710-13/+1691
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* radeonsi: Float format fixups.Michel Dänzer2012-09-071-1/+24
| | | | | | Fixes piglit spec/ARB_texture_float/fbo-generatemipmap-formats. Signed-off-by: Michel Dänzer <[email protected]>
* radeonsi: Handle more SNORM formats.Michel Dänzer2012-09-071-0/+22
| | | | | | | Fixes piglit spec/EXT_texture_snorm/fbo-generatemipmap-formats (except for what seems like a random fluke). Signed-off-by: Michel Dänzer <[email protected]>
* radeonsi: Handle TGSI_SEMANTIC_FOG.Michel Dänzer2012-09-071-0/+1
| | | | | | | | | Fixes exponential fog. The pixel shaders for linear fog seem to get miscompiled still somehow. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Match fexp2 for SI.Michel Dänzer2012-09-071-1/+3
| | | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g: order atom emission v3Jerome Glisse2012-09-067-82/+116
| | | | | | | | | | | | | To avoid GPU lockup registers must be emited in a specific order (no kidding ...). This patch rework atom emission so order in which atom are emited in respect to each other is always the same. We don't have any informations on what is the correct order so order will need to be infered from fglrx command stream. v2: add comment warning that atom order should not be taken lightly v3: rebase on top of alphatest atom fix Signed-off-by: Jerome Glisse <[email protected]>
* r600g: fix num of dwords needed for alphatest_state atomJerome Glisse2012-09-061-1/+1
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* llvmpipe: Make driver name more informative.José Fonseca2012-09-061-1/+4
| | | | | | | | | | | | | | | Such as "llvmpipe (LLVM 3.1, 128 bits)" or "llvmpipe (LLVM 3.1, 256 bits)" when leveraging AVX 8-wide registers. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi: Handle more L/I/A format cases.Michel Dänzer2012-09-061-0/+14
| | | | | | | Fixes piglit fbo-generatemipmap-formats. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Enable whole quad mode for pixel shaders.Michel Dänzer2012-09-061-2/+10
| | | | | | | Fixes wrong mipmap level being sampled at some triangle edges. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Add intrinsic for enabling whole quad mode in SI pixel shaders.Michel Dänzer2012-09-064-0/+23
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: SI shader vector instructions implicitly use the EXEC register.Michel Dänzer2012-09-061-0/+4
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Extend SI EXEC register support.Michel Dänzer2012-09-062-2/+7
| | | | | | | Add 32 bit lo and hi variants, and binary encodings. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Remove R600InstrInfo.td from TD_FILESTom Stellard2012-09-061-1/+0
| | | | | Fixes build bug introduced by cebbdd4ac23725963207bf6f8fc7101150e6065f
* radeonsi: Enable NPOT textures again.Michel Dänzer2012-09-061-1/+1
| | | | | | | | Should be at least mostly working now (with the corresponding fixes in libdrm_radeon). Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: Mipmaps require memory footprint to be padded to powers of two.Michel Dänzer2012-09-061-0/+1
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: Sampler view state simplification.Michel Dänzer2012-09-061-11/+9
| | | | | | | | We can always use the offset and tiling mode from level 0 and restrict the first and last mipmap level to be used in the sampler resource. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: Untiled textures are linear aligned, not linear general.Michel Dänzer2012-09-061-3/+3
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/llvm: Cleanup makefileTom Stellard2012-09-062-13/+37
| | | | | Hopefully, this will fix all the parallel make problems people have been having.
* Remove useless checks for NULL before freeingMatt Turner2012-09-0510-43/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Same as earlier commit, except for "FREE" This patch has been generated by the following Coccinelle semantic patch: // Remove useless checks for NULL before freeing // // free (NULL) is a no-op, so there is no need to avoid it @@ expression E; @@ + FREE (E); + E = NULL; - if (unlikely (E != NULL)) { - FREE(E); ( - E = NULL; | - E = 0; ) ... - } @@ expression E; type T; @@ + FREE ((T) E); + E = NULL; - if (unlikely (E != NULL)) { - FREE((T) E); ( - E = NULL; | - E = 0; ) ... - } @@ expression E; @@ + FREE (E); - if (unlikely (E != NULL)) { - FREE (E); - } @@ expression E; type T; @@ + FREE ((T) E); - if (unlikely (E != NULL)) { - FREE ((T) E); - } Reviewed-by: Brian Paul <[email protected]>
* Remove useless checks for NULL before freeingMatt Turner2012-09-051-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch has been generated by the following Coccinelle semantic patch: // Remove useless checks for NULL before freeing // // free (NULL) is a no-op, so there is no need to avoid it @@ expression E; @@ + free (E); + E = NULL; - if (unlikely (E != NULL)) { - free(E); ( - E = NULL; | - E = 0; ) ... - } @@ expression E; type T; @@ + free ((T) E); + E = NULL; - if (unlikely (E != NULL)) { - free((T) E); ( - E = NULL; | - E = 0; ) ... - } @@ expression E; @@ + free (E); - if (unlikely (E != NULL)) { - free (E); - } @@ expression E; type T; @@ + free ((T) E); - if (unlikely (E != NULL)) { - free ((T) E); - } Reviewed-by: Brian Paul <[email protected]>
* Don't cast the return value of malloc/reallocMatt Turner2012-09-054-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch has been generated by the following Coccinelle semantic patch: // Don't cast the return value of malloc/realloc. // // Casting the return value of malloc/realloc only stands to hide // errors. @@ type T; expression E1, E2; @@ - (T) ( _mesa_align_calloc(E1, E2) | _mesa_align_malloc(E1, E2) | calloc(E1, E2) | malloc(E1) | realloc(E1, E2) )
* radeon/llvm: Fix operand ordering for V_CNDMASK_B32Tom Stellard2012-09-051-3/+3
| | | | This fixes several hundred piglit tests.
* radeon/llvm: Use correct float->int conversion opcode on SI.Tom Stellard2012-09-051-2/+4
| | | | | V_CVT_I32_F32 converts floats to signed integers, but we were using V_CVT_F32_I32 which convertes signed integers to float.
* radeon/llvm: Fix lowering of SI_V_CNDLTTom Stellard2012-09-041-3/+3
| | | | | SREG_LIT_0 is a scalar register, so it can only be used in the first argument of vector instructoins.
* radeon/llvm: Fix encoding of V_CNDMASK_B32Tom Stellard2012-09-042-4/+4
| | | | | | | The CodeEmitter was not setting the VGPR bit for src0, because the instruction definition had the VCC register in the src0 slot, instead of the actual src0 register. This has been fixed by moving the VCC register to the end of the operand list.
* radeon/llvm: do not convert f32 operand of select_cc nodeVincent Lejeune2012-09-041-20/+20
| | | | | | v2:-use camel coding style Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 (bool)Vincent Lejeune2012-09-042-2/+26
| | | | | | v2:-wrap line at 80 characters Reviewed-by: Tom Stellard <[email protected]>
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