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* i915g: Add blitter_context argument.Vinson Lee2017-06-081-1/+1
* etnaviv: flush resource when binding as sampler viewLucas Stach2017-06-081-0/+3
* etnaviv: don't flush resource to self without TSLucas Stach2017-06-081-1/+1
* etnaviv: upgrade DISCARD_RANGE to DISCARD_WHOLE_RESOURCE if possibleLucas Stach2017-06-081-0/+14
* etnaviv: simplify transfer tiling handlingLucas Stach2017-06-081-41/+29
* etnaviv: don't read back resource if transfer discards contentsLucas Stach2017-06-081-1/+3
* etnaviv: honor PIPE_TRANSFER_UNSYNCHRONIZED flagLucas Stach2017-06-081-12/+23
* etnaviv: slim down resource waitingLucas Stach2017-06-084-23/+6
* radeonsi: Use libdrm to get chipset nameSamuel Li2017-06-072-1/+12
* util: Port nir_array functionality to u_dynarrayThomas Helland2017-06-075-7/+7
* gallium: Add missing includesThomas Helland2017-06-072-0/+2
* radeonsi: update clip_regs on shader state changes only when it's neededMarek Olšák2017-06-071-3/+32
* radeonsi: precompute some fields for PA_CL_VS_OUT_CNTL in si_shader_selectorMarek Olšák2017-06-074-16/+25
* radeonsi: add a new helper si_get_vsMarek Olšák2017-06-072-17/+19
* radeonsi: isolate real framebuffer changes from the decompression passes (v3)Samuel Pitoiset2017-06-073-2/+28
* radeonsi: do EarlyCSEMemSSA LLVM passMarek Olšák2017-06-071-0/+2
* radeonsi: remove 8 bytes from si_shader_keyMarek Olšák2017-06-073-14/+17
* radeonsi: move PSIZE and CLIPDIST unique IO indices after GENERICMarek Olšák2017-06-072-8/+14
* svga: Always set the alpha value to 1 when sampling using an XRGB viewThomas Hellstrom2017-06-071-13/+30
* svga: Fix imported surface view creationThomas Hellstrom2017-06-074-11/+33
* svga: Set alpha to 1 for non-alpha viewsThomas Hellstrom2017-06-071-0/+18
* svga: Allow format differences in 16-bit RGBA surface sharingThomas Hellstrom2017-06-071-1/+5
* radeonsi: clean up decompress blend state namesMarek Olšák2017-06-074-10/+10
* gallium/radeon: clean up a misleading statement from the old daysMarek Olšák2017-06-071-4/+1
* radeonsi: don't use 1D tiling for Z/S on VI to get TC-compatible HTILEMarek Olšák2017-06-071-3/+13
* radeonsi: enable TC-compatible stencil compression on VIMarek Olšák2017-06-073-5/+8
* radeonsi/gfx9: prevent a race when the previous shader's main part is missingMarek Olšák2017-06-071-0/+2
* radeonsi/gfx9: wait for main part compilation of 1st shaders of merged shadersMarek Olšák2017-06-071-0/+4
* radeonsi/gfx9: fix LS scratch buffer support without TCS for GFX9Marek Olšák2017-06-071-3/+18
* radeonsi: move streamout state update out of si_update_shadersMarek Olšák2017-06-072-16/+25
* radeonsi: remove dead code in declare_input_fsMarek Olšák2017-06-071-5/+0
* radeonsi: move handling of DBG_NO_OPT_VARIANT into si_shader_selector_keyMarek Olšák2017-06-071-4/+3
* radeonsi: use a compiler queue with a low priority for optimized shadersMarek Olšák2017-06-073-8/+34
* util/u_queue: add an option to set the minimum thread priorityMarek Olšák2017-06-072-2/+2
* radeonsi: decrease the number of compiler threads to num CPUs - 1Marek Olšák2017-06-071-1/+4
* radeonsi: drop unfinished shader compilations when destroying shadersMarek Olšák2017-06-072-3/+5
* freedreno/a5xx: set SP_BLEND_CONTROL properlyRob Clark2017-06-073-1/+4
* freedreno/a5xx: LRZ supportRob Clark2017-06-0714-14/+234
* freedreno: drop timestamp fieldRob Clark2017-06-072-3/+0
* freedreno/a5xx: refactor out helper for LRZ flushRob Clark2017-06-073-11/+19
* freedreno: reshuffle FD_MESA_DEBUG bitmaskRob Clark2017-06-071-3/+3
* freedreno: update generated headersRob Clark2017-06-077-17/+31
* gallium/u_blitter: use 2D_ARRAY for cubemap blits if possibleMarek Olšák2017-06-073-3/+3
* tree-wide: remove trailing backslashEric Engestrom2017-06-073-4/+4
* radeonsi: fix a GPU hang with tessellation on 2-CU configsMarek Olšák2017-06-061-1/+5
* radeon: remove out of date LLVM_REVISION.txtEmil Velikov2017-06-052-4/+0
* r600: refactor out some compressed resource state code.Dave Airlie2017-06-061-24/+28
* r600: document some of the missing shader constants.Dave Airlie2017-06-061-0/+4
* r600: add register info for atomic counters.Dave Airlie2017-06-062-0/+51
* r600: add missing RAT registers and operations.Dave Airlie2017-06-063-0/+59
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