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* radeonsi: don't pass scratch buffer to user SGPRsBas Nieuwenhuizen2016-04-191-8/+0
| | | | | | | | As far as I can see we use relocations for clover too. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: split input upload off from si_launch_gridBas Nieuwenhuizen2016-04-191-41/+52
| | | | | | | | | | | | | | | | Also uses a dynamically allocated buffer using u_upload_alloc. The old buffer per program approach required serializing all dispatches of the same program. v2: - Clarified commit message. - Use radeon_set_sh_reg_seq. - Also upload input buffer for clover kernels, even when input_size is 0, as it contains grid parameters. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* radeonsi: implement TGSI compute shader creationBas Nieuwenhuizen2016-04-191-18/+58
| | | | | | | v2: Moved scratch_enabled initialization after compile. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: update shader count for compute shadersBas Nieuwenhuizen2016-04-191-1/+2
| | | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set maximum work group size based on block sizeBas Nieuwenhuizen2016-04-191-0/+12
| | | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: implement shared atomicsBas Nieuwenhuizen2016-04-191-1/+76
| | | | | | | | | | v2: - Use single region - Use get_memory_ptr Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* radeonsi: implement shared memory load/storeBas Nieuwenhuizen2016-04-191-2/+82
| | | | | | | | | | v2: - Use single region - Combine address calculation Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* radeonsi: add shared memoryBas Nieuwenhuizen2016-04-194-0/+37
| | | | | | | | | | | | | | | Declares the shared memory as a global variable so that LLVM is aware of it and it does not conflict with passes like AMDGPUPromoteAlloca. v2: - Use ctx->i8. - Dropped null-check for declare_memory_region. - Changed memory region array to single region. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* radeonsi: lower compute shader argumentsBas Nieuwenhuizen2016-04-192-0/+50
| | | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: Use CE for all descriptors.Bas Nieuwenhuizen2016-04-191-10/+64
| | | | | | | | | | v2: Load previous list for new CS instead of re-emitting all descriptors. v3: Do radeon_add_to_buffer_list in si_ce_upload. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Replace list_dirty with a mask.Bas Nieuwenhuizen2016-04-192-17/+29
| | | | | | | We can then upload only the dirty ones with the constant engine. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Add CE uploader.Bas Nieuwenhuizen2016-04-193-0/+37
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Allocate chunks of CE ram.Bas Nieuwenhuizen2016-04-192-9/+27
| | | | | | | | | v2: Use 32 byte alignment. v3: Don't allocate CE space for vertex buffer descriptors. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Add CE synchronization.Bas Nieuwenhuizen2016-04-192-0/+27
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Add CE packet definitions.Bas Nieuwenhuizen2016-04-191-0/+6
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Create CE IB.Bas Nieuwenhuizen2016-04-195-1/+54
| | | | | | | | | | | | | | | | | | | Based on work by Marek Olšák. v2: Add preamble IB. Leaves the load packet in the space calculation as the radeon winsys might not be able to support a premable. The added space calculation may look expensive, but is converted to a constant with (at least) -O2 and -O3. v3: - Fix code style. - Remove needed space for vertex buffer descriptors. - Fail when the preamble cannot be created. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: Add support for const IB.Marek Olšák2016-04-191-0/+30
| | | | | | v2: Use the correct IB to update request (Bas Nieuwenhuizen) v3: Add preamble IB. (Bas Nieuwenhuizen) Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: move ring_type into winsysesMarek Olšák2016-04-191-1/+0
| | | | | | Not used by drivers. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* llvmpipe: Call LLVMShutdown before exiting.Jose Fonseca2016-04-191-0/+2
| | | | | | So that LLVM frees its globals. Trivial.
* llvmpipe: Avoid LLVMGetGlobalContext in tests.Jose Fonseca2016-04-195-6/+24
| | | | Trivial.
* llvmpipe: Skip false exp2 failure in lp_test_arit due to buggy MSVCRT.Jose Fonseca2016-04-191-4/+34
| | | | | | | | | 64bits MSVCRT's exp2f(-inf) returns -inf instead of 0. Tested with MSVC 2013's CRT. (I haven't tried 2015 yet.) Also this does not happen with MinGW. Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: Test more vector lengths.Jose Fonseca2016-04-191-13/+30
| | | | | | | | | | All power of two of up native vector length. There is actually a bug in lp_build_round for v2, whereby it doesn't round to nearest. Fixing is left to the future, but the test is now able to expect it to fail. Reviewed-by: Roland Scheidegger <[email protected]>
* Revert "nv50/ra: `isinf()` is in namespace `std` since C++11."Jose Fonseca2016-04-191-4/+0
| | | | | | This reverts commit f525db6358fbaa7b4296d2e6484e0b1ae703ac78. It was superseeded by commit 649704f1f7c9e1d0990d34a76154b2eb656bee42.
* vc4: Fix fbo-generatemipmap-formats for NPOT.Eric Anholt2016-04-181-0/+20
| | | | | | | Single-sampled texture miplevels > 1 are stored in POT-aligned areas, but we only get one value to control the stride of the src and dst for single sampled buffers. A RCL tile blit from level != 1 to level == 0 would therefore load from the wrong stride.
* vc4: Remove unused "immediates" fieldEric Anholt2016-04-181-1/+0
| | | | This was for TGSI, which we no longer have to deal with.
* gallivm: convert size query to using a set of parameters.Dave Airlie2016-04-192-36/+8
| | | | | | | | | | This isn't currently that easy to expand, so fix it up before expanding it later to include dynamic samplers. [airlied: use some local variables (Roland)] Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* swr: dereference cbuf/zbuf/views on context destroyTim Rowley2016-04-181-0/+15
| | | | | | Fixes resource memory leaks. Reviewed-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: fix grouping issue w/ reverse swizzlesRob Clark2016-04-181-1/+17
| | | | | | | | | | | | | | | | | | | | | | | When we have something like: MOV OUT[n], IN[m].wzyx the existing grouping code was missing a potential conflict. Due to input needing to be sequential scalar regs, we have: IN: x <-> y <-> z <-> w which would be grouped to: OUT: w <-> z2 <-> y2 <-> x (where the 2 denotes a copy/mov) but that can't actually work. We need to realize that x and w are already in the same chain, not just that they aren't both already in new chain being built. With this fixed, we probably no longer need the hack from f68f6c0. Signed-off-by: Rob Clark <[email protected]>
* radeonsi: use enums in si_shader.hMarek Olšák2016-04-181-93/+119
| | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: use enums in r600_query.hMarek Olšák2016-04-181-20/+23
| | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: always use PFP_SYNC_ME when doing flushes and waitsMarek Olšák2016-04-182-1/+10
| | | | | | This is typically used by the closed driver before SURFACE_SYNC. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't do VS/PS partial flushes if SURFACE_SYNC waits tooMarek Olšák2016-04-181-11/+14
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add safety assertions for meta cache flushesMarek Olšák2016-04-181-0/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't use ACQUIRE_MEM on the graphics ringMarek Olšák2016-04-181-18/+8
| | | | | | | | | It's only required on the compute ring. This matches the closed driver. The compute flag is removed to prevent confusion and Bas's compute shader patches remove it in the whole function. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove TODO and correct a comment in si_emit_cache_flushMarek Olšák2016-04-181-2/+1
| | | | | | Yes, that flag is really needed. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't flush CB/DB caches for performance countersMarek Olšák2016-04-181-3/+6
| | | | | | | | I'm not sure about this. This will make the engines go idle, but the caches will be unflushed. This should match app behavior without performance counters, which can be a good thing. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: don't flush CB/DB caches for timestamp queriesMarek Olšák2016-04-182-2/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: fix Nine with its slightly shifted viewportsMarek Olšák2016-04-181-15/+21
| | | | | | | just need to do the calculation in floating-point and then round things properly Reviewed-by: Axel Davy <[email protected]>
* vc4: Add support for rendering to cube map surfaces.Eric Anholt2016-04-181-1/+2
| | | | | | | We need to fix up the offset to point at the face of the cube. Fixes piglit fbo-cubemap, copyteximage CUBE, and glean's fbo test. Cc: "11.1 11.2" <[email protected]>
* vc4: Don't flush on read-only access of buffers read by the CL.Eric Anholt2016-04-183-7/+16
| | | | | | Fixes piglit mixed-immediate-and-vbo, and may significantly improve performance of applications that store a 4-byte IB in the same VBO as vertex data.
* vc4: Sanity check that flushes don't happen between state emit and draw.Eric Anholt2016-04-181-0/+7
| | | | | | Catches the cause of failure in arb_vertex_buffer_object-mixed-immediate-and-vbo, I've had this class of failure before, and it probably won't be the last time.
* vc4: Sanity check strides for imported BOs.Eric Anholt2016-04-181-5/+18
| | | | | | | If we're going to sample from or render to them at some particular size, we'd better make sure that they actually are that size. Causes some tests under simulation to generate appropriate error messages instead of failures.
* r600g: Move R600_BIG_ENDIAN to r600_pipe_common.hOded Gabbay2016-04-182-6/+6
| | | | | | | | I need to do this so I could use R600_BIG_ENDIAN in files which include r600_pipe_common.h but not r600_pipe.h Signed-off-by: Oded Gabbay <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: fix code indentationOded Gabbay2016-04-182-10/+10
| | | | | Signed-off-by: Oded Gabbay <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: handle vertex shaders that disable clipping & viewportMarek Olšák2016-04-162-1/+20
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* llvmpipe: (trivial) initialize src1_alpha var to NULLRoland Scheidegger2016-04-151-1/+1
| | | | | | | | | | | The blend code would do a conditional assignment based on it, causing valgrind to complain. Since that variable was actually unused in this case, this doesn't fix anything but the warning. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94955 Cc: "11.1 11.2" <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium/swr: confine c++11 flag to swr driverTim Rowley2016-04-151-2/+3
| | | | | | | | On the philosophy that a driver shouldn't change the compile flags for the entire tree, take the clove approach of moving the c++11 flag to the swr driver directory. Reviewed-by: Emil Velikov <[email protected]>
* gallium/swr: allow swr use as a swrast dri driverTim Rowley2016-04-151-0/+8
| | | | | Reviewed-by: Emil Velikov <[email protected]> Tested-by: Ilia Mirkin <[email protected]>
* vc4: Fix subimage accesses to LT textures.Eric Anholt2016-04-151-4/+4
| | | | | | | | | | | | | This code started out like the T case, iterating over utile offsets, but I had partially switched it to iterating over pixel offsets. I hadn't caught this before because it's unusual to do piecemeal uploads to small textures. Fixes bad text rendering in QT5 apps, which use a 256x16 glyph cache. Also fixes 6 piglit tests related to glTexSubImage() and glGetTexSubImage(). Cc: "11.1 11.2" <[email protected]>
* radeon/uvd: fix tonga feedback buffer sizeLeo Liu2016-04-141-4/+8
| | | | | | | | This only applies to tonga Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Cc: "11.1 11.2" <[email protected]>
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