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* radeon/llvm: Fix operand ordering for V_CNDMASK_B32Tom Stellard2012-09-051-3/+3
* radeon/llvm: Use correct float->int conversion opcode on SI.Tom Stellard2012-09-051-2/+4
* radeon/llvm: Fix lowering of SI_V_CNDLTTom Stellard2012-09-041-3/+3
* radeon/llvm: Fix encoding of V_CNDMASK_B32Tom Stellard2012-09-042-4/+4
* radeon/llvm: do not convert f32 operand of select_cc nodeVincent Lejeune2012-09-041-20/+20
* radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 (bool)Vincent Lejeune2012-09-042-2/+26
* radeon/llvm: support setcc on f32Vincent Lejeune2012-09-041-9/+27
* radon/llvm: br_cc f32 now lowered without castVincent Lejeune2012-09-041-9/+24
* radeon/llvm: swap wrong OPCODE_IS_*_ZERO_* opcode and useVincent Lejeune2012-09-042-4/+4
* radeonsi: stop big offsets from hanging the GPU v2Christian König2012-09-041-2/+9
* radeonsi: adjust PIPE_SHADER_CAP_MAX_CONSTSChristian König2012-09-042-5/+2
* radeon/llvm: fix SelectADDR8BitOffsetChristian König2012-09-041-1/+1
* r600g: adjust QUANT_MODE for higher precisionVadim Girlin2012-09-044-2/+24
* radeonsi: disable array-textures for nowChristian König2012-09-031-1/+1
* radeonsi: disable Z16 for nowChristian König2012-09-031-2/+2
* radeonsi: disable NPOT textures for nowChristian König2012-09-031-1/+1
* radeonsi: handle indirect constants gracefullyChristian König2012-09-031-0/+7
* radeon/llvm: Rework how immediate operands are handled with SITom Stellard2012-08-3110-44/+150
* radeon/llvm: Fix typo in assertTom Stellard2012-08-311-1/+1
* radeon/llvm: Fix isEG tablegen predicateTom Stellard2012-08-311-3/+5
* radeon/llvm: Add support for RCP instruction on SITom Stellard2012-08-311-1/+3
* radeon/llvm: Support AMDGPUfmin DAG node on SITom Stellard2012-08-311-1/+3
* radeonsi: Handle TGSI_SEMANTIC_PSIZETom Stellard2012-08-311-0/+1
* r600g: enable transform feedback on CaymanMarek Olšák2012-08-311-3/+1
* r600g: implement MSAA for CaymanMarek Olšák2012-08-316-72/+184
* r600g: enable MSAA on r6xx by defaultMarek Olšák2012-08-301-3/+6
* r600g: disable MSAA depth decompression on r6xxMarek Olšák2012-08-301-1/+10
* r600g: implement color resolve for r600Marek Olšák2012-08-307-26/+199
* r600g: fix CB_SHADER_MASK and CB_TARGET_MASK for r6xxMarek Olšák2012-08-301-11/+24
* r600g: implement draw_rectangle callbackMarek Olšák2012-08-303-2/+72
* r600g: implement MSAA for r700Marek Olšák2012-08-307-41/+262
* r600g: change programming of CB_SHADER_MASK on r600-r700Marek Olšák2012-08-301-1/+2
* radeonsi: fix stupid bug added in commit 07838603b9a69c05911edbcd351bfce5ad9b...Christian König2012-08-301-7/+8
* radeon/llvm: Fix encoding of FP immediates on SITom Stellard2012-08-291-1/+6
* radeon/llvm: Create a register class for the M0 registerTom Stellard2012-08-295-16/+24
* radeon/llvm: Set the neverHasSideEffects bit on more instructionsTom Stellard2012-08-291-0/+2
* radeon/llvm: Declare the interpolation intrinsics as ReadOnlyTom Stellard2012-08-293-3/+4
* radeon/llvm: Mark M0 as a def when lowering interpolation instructionsTom Stellard2012-08-291-4/+2
* radeon/llvm: Handle TGSI KIL opcode for SI.Michel Dänzer2012-08-283-0/+44
* radeon/llvm: Basic support for SI EXEC register.Michel Dänzer2012-08-283-2/+23
* radeonsi: Don't write to the PA_SC_RASTER_CONFIG register.Michel Dänzer2012-08-281-1/+0
* r600g: fix relative addressing on RS780 and RS880Marek Olšák2012-08-281-7/+6
* llvmpipe: Bump the maximum texture size (in pixels).José Fonseca2012-08-282-2/+9
* r300g: implement TRUNC correctlyMarek Olšák2012-08-274-1/+42
* radeonsi: Use FP16 shader export format when necessary / possible.Michel Dänzer2012-08-276-18/+114
* radeonsi: Refactor initialization of shader export intrinsic arguments.Michel Dänzer2012-08-271-36/+48
* radeonsi: Maintain cache of pixel shader variants according to contxt state.Michel Dänzer2012-08-276-59/+210
* radeonsi: Drop extraneous semicolons from pm4 state macro definitions.Michel Dänzer2012-08-271-3/+3
* r600g: implement compression for MSAA colorbuffers for evergreenMarek Olšák2012-08-2710-19/+479
* r600g: cleanup names around depth decompressionMarek Olšák2012-08-275-24/+24
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