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* ilo: add support for PIPE_QUERY_PIPELINE_STATISTICSChia-I Wu2014-03-104-3/+108
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* ilo: add ILO_3D_PIPELINE_WRITE_STATISTICSChia-I Wu2014-03-105-0/+90
| | | | The command writes statistics registers to the specified bo.
* ilo: add some MI commands to GPEChia-I Wu2014-03-104-0/+116
| | | | We will need MI commands that load/store registers.
* ilo: set PIPE_CONTROL_GLOBAL_GTT_WRITE automaticallyChia-I Wu2014-03-102-2/+16
| | | | | Set the flag automatically in gen6_emit_PIPE_CONTROL(), and set it only for GEN6.
* ilo: print a warning when PPGTT is disabledChia-I Wu2014-03-102-0/+20
| | | | | Despite what the PRMs say, the driver appears to work fine when PPGTT is disabled. But at least print a warning in that case.
* ilo: require hardware logical context supportChia-I Wu2014-03-105-12/+12
| | | | The code paths are not tested for a while, and have some known issues.
* ilo: move ring types to winsysChia-I Wu2014-03-106-34/+11
| | | | | It results in less code despite that i915_drm.h specifies the ring type as part of the execution flags.
* ilo: winsys may limit the batch buffer sizeChia-I Wu2014-03-105-4/+12
| | | | | | The maximum batch buffer size is determined at the time of drm_intel_bufmgr_gem_init(). Make sure the pipe driver does not exceed the limit.
* ilo: PIPE_CAP_QUERY_TIMESTAMP may not be supportedChia-I Wu2014-03-102-1/+4
| | | | Reading TIMESTAMP register may fail, depending on both kernel and hardware.
* ilo: rework winsys batch buffer functionsChia-I Wu2014-03-103-16/+11
| | | | | | | | | | | Rename intel_winsys_check_aperture_size() to intel_winsys_can_submit_bo(), intel_bo_exec() to intel_winsys_submit_bo(), and intel_winsys_decode_commands() to intel_winsys_decode_bo(). Make a semantic change to ignore intel_context when the ring is not the render ring.
* ilo: replace bo alloc flags by initial domainsChia-I Wu2014-03-106-14/+16
| | | | | | The only alloc flag is INTEL_ALLOC_FOR_RENDER, which can as well be expressed by specifying the initial write domain. The change makes it obvious that we failed to set INTEL_ALLOC_FOR_RENDER in several places.
* ilo: remove intel_bo_get_size()Chia-I Wu2014-03-102-14/+18
| | | | | | Commit bfa8d21759c5f2b5b0885c696842167bd4c64fee uses it to work around a hardware limitation. But there are other ways to do it without the need for intel_bo_get_size().
* ilo: remove intel_bo_get_virtual()Chia-I Wu2014-03-104-90/+105
| | | | Make the map functions return the pointer directly.
* ilo: rework winsys bo reloc functionsChia-I Wu2014-03-104-8/+13
| | | | | | | | | | | | | Rename intel_bo_emit_reloc() to intel_bo_add_reloc(), intel_bo_clear_relocs() to intel_bo_truncate_relocs(), and intel_bo_references() to intel_bo_has_reloc(). Besides, we need intel_bo_get_offset() only to get the presumed offset afer adding a reloc entry. Remove the function and make intel_bo_add_reloc() return the presumed offset. While at it, switch to gem_bo->offset64 from gem_bo->offset.
* ilo: remove intel_winsys_enable_reuse()Chia-I Wu2014-03-101-2/+0
| | | | It should be an (winsys) implementation detail.
* radeonsi: Use proper member name for deleting export shader PM4 stateMichel Dänzer2014-03-101-0/+2
| | | | | | Fixes double-free with some piglit tests using geometry shaders. Reviewed-by: Marek Olšák <[email protected]>
* r600g: document why texture offset emulation is neededMarek Olšák2014-03-101-1/+2
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* Revert nvc0 part of "nv50: adjust blit_3d handling of ms output textures"Ilia Mirkin2014-03-091-8/+4
| | | | | | | | The nvc0 bits don't appear to work, and I thought I had removed them from the commit. Oops. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.0 10.1" <[email protected]>
* nv50: adjust blit_3d handling of ms output texturesIlia Mirkin2014-03-092-8/+16
| | | | | | | | This fixes some unwanted scaling when the output is multisampled. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Christoph Bumiller <[email protected]> Cc: "10.0 10.1" <[email protected]>
* nouveau: fix fence waiting logic in screen destroyIlia Mirkin2014-03-093-7/+27
| | | | | | | | | | | | nouveau_fence_wait has the expectation that an external entity is holding onto the fence being waited on, not that it is merely held onto by the current pointer. Fixes a use-after-free in nouveau_fence_wait when used on the screen's current fence. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75279 Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Christoph Bumiller <[email protected]> Cc: "9.2 10.0 10.1" <[email protected]>
* nouveau: add valid range tracking to nouveau_bufferIlia Mirkin2014-03-096-0/+47
| | | | | | | | | This logic is borrowed from the radeon code. The transfer logic will only get called for PIPE_BUFFER resources, so it shouldn't be necessary to worry about them becoming render targets. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Christoph Bumiller <[email protected]>
* radeonsi: fix freeing descriptor buffersChristian König2014-03-081-1/+1
| | | | | | | | That structure member is a pointer, so the loop with the Elements macro only freed up the first entry. Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix leaking the bound state on destruction v2Christian König2014-03-083-0/+10
| | | | | | | v2: rebased on stale pointer fixes Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: avoid stale state pointersChristian König2014-03-081-9/+3
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: avoid stale pointers in si_delete_shader_selectorChristian König2014-03-081-1/+6
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon/vce: fix memory leakChristian König2014-03-081-0/+1
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon: Include radeon_elf_util.c in the list of LLVM_C_FILES v2Tom Stellard2014-03-072-1/+2
| | | | | | | | | | | | | | | | | This fixes the a build breakage caused by 6974eb907600b9d0176d3158ff0fd30ac3e56a55 on build configurations where all the following are true: 1. radeonsi is not being built 2. r600g is being built 3. opencl is disabled 4. --enable-r600-llvm-compiler is not being used 5. libelf is not installed v2: - Add $(RADEON_CFLAGS) to libllvmradeon_la_CFLAGS Tested-by: Brian Paul <[email protected]>
* radeon/llvm: Factor elf parsing code out into its own functionTom Stellard2014-03-074-51/+132
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon: Rename struct radeon_llvm_binary to radeon_shader_binary v2Tom Stellard2014-03-075-12/+23
| | | | | | | | | | And move its definition into r600_pipe_common.h; This struct is a just a container for shader code and has nothing to do with LLVM. v2: - Drop unrelated Makefile change Reviewed-by: Michel Dänzer <[email protected]>
* gallium: rename R4A4 and A4R4 formats to match their swizzleMarek Olšák2014-03-071-1/+1
| | | | | | Like L4A4. Reviewed-by: Brian Paul <[email protected]>
* radeonsi: fix blit compressed texture workaround to support 2D arraysMarek Olšák2014-03-071-1/+2
| | | | | | We don't have a piglit test for this, but I think it's correct. Reviewed-by: Michel Dänzer <[email protected]>
* r600g: fix blitting the last 2 mipmap levels for EvergreenMarek Olšák2014-03-073-13/+36
| | | | | | | | This fixes a lot of compressedteximage piglit tests. R600-R700 don't have this issue. Cc: [email protected]
* r600g: fix texelFetchOffset GLSL functionsMarek Olšák2014-03-071-10/+77
| | | | Cc: [email protected]
* radeon: Use upload manager for buffer downloadsNiels Ole Salscheider2014-03-071-18/+56
| | | | | | | Using DMA for reads is much faster. Signed-off-by: Niels Ole Salscheider <[email protected]> Signed-off by: Marek Olšák <[email protected]>
* WIP: freedreno/a3xx: incorrect scissor for binning passRob Clark2014-03-053-8/+35
| | | | | | | | | | | | | If scissor optimization is used (to avoid bringing scissored portions of the render target into GMEM and then back out to system memory) in combination with hw binning pass, the result would be a scissor mismatch between binning pass and rendering pass. This would cause rendering bugs in some scenarios with (for example) gnome-shell. I would have expected that simply using the correct screen-scissor during the binning pass would be enough, but seems like there is something else missing. So for now disable binning pass if scissor optimization is used.
* nv50,nvc0: add 11f_11f_10f vertex supportIlia Mirkin2014-03-043-1/+3
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* radeon/uvd: fix typo in documentationDieter Nützel2014-03-041-1/+1
| | | | | | s/grap/grab/ Signed-off-by: Alex Deucher <[email protected]>
* r600g: implement edge flagsMarek Olšák2014-03-043-4/+53
| | | | | Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* r600g: port color buffer format conversion from radeonsiMarek Olšák2014-03-044-913/+161
| | | | | | | | | | | | r600_translate_colorformat is rewritten to look like radeonsi. r600_translate_colorswap is shared with radeonsi. r600_colorformat_endian_swap is consolidated. This adds some formats which were missing. Future "plain" formats will automatically be supported. Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: move translate_colorswap to common codeMarek Olšák2014-03-044-54/+62
| | | | | | | Also translate the Y__X swizzle. Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* softpipe: use 64-bit arithmetic in softpipe_resource_layout()Brian Paul2014-03-031-3/+3
| | | | | | | | To avoid 32-bit integer overflow for large textures. Note: we're already doing this in llvmpipe. Cc: "10.0" "10.1" <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* freedreno/a3xx/compiler: overflow in trans_endifRob Clark2014-03-021-13/+5
| | | | | | | | The logic to count number of block outputs was out of sync with the actual array construction. But to simplify / make things less fragile, we can just allocate the arrays for worst case size. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: fix for resolving PHI'sRob Clark2014-03-021-18/+33
| | | | | | | A value may be assigned on only one side of an if/else. In this case we can simply substitute a mov.f32f32. Signed-off-by: Rob Clark <[email protected]>
* freedreno/lowering: two-sided-colorRob Clark2014-03-025-57/+269
| | | | | | | | | Add option to generate fragment shader to emulate two sided color. Additional inputs are added to shader for BCOLOR's (on corresponding to each COLOR input). CMP instructions are used to select whether to use COLOR or BCOLOR. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: add SSGRob Clark2014-03-022-0/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix gl_PointSizeRob Clark2014-03-025-13/+20
| | | | | | | If vertex writes pointsize, there are a few extra bits we need to turn on in the cmdstream here and there. Signed-off-by: Rob Clark <[email protected]>
* freedreno: resync generated headersRob Clark2014-03-024-5/+7
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: binning-pass vertex shader variantRob Clark2014-03-023-18/+57
| | | | | | | | | | | Now that we have the infrastructure for shader variants, add support to generate an optimized shader for hw binning pass (with varyings/outputs other than position/pointsize removed). This exposes the possibility that the shader uses fewer constants than what is bound, so we have to take care to not emit consts beyond what the shader uses, lest we provoke the wrath of the HLSQ lockup! Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: add support for frag coord/faceRob Clark2014-03-027-123/+408
| | | | | | | Fixes anything that tries to use gl_FrontFacing/gl_FragCoord. Also, face support is needed to emulate two sided color. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix for unused inputsRob Clark2014-03-022-5/+11
| | | | | | | An unused input might not have a register assigned. We don't want bogus regid to result in impossibly high max_reg.. Signed-off-by: Rob Clark <[email protected]>
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