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* radeon/llvm: Remove AMDILTargetMachineTom Stellard2012-05-2919-363/+90
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* nouveau: unreference fences on resource destructionChristoph Bumiller2012-05-292-0/+6
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* nvc0: optimize blend cso by checking which by-RT data actually differsChristoph Bumiller2012-05-291-65/+94
| | | | Can save about 200 bytes of command buffer space.
* nvc0: don't upload UCPs if the shader doesn't use themChristoph Bumiller2012-05-291-1/+1
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* nvc0/ir: allow 64-bit constant loads on nve4Christoph Bumiller2012-05-292-1/+3
| | | | Looks like only 128-bit access doesn't work.
* nvc0/ir: fix texture barrier insertion to prevent WAW hazardsChristoph Bumiller2012-05-296-29/+88
| | | | Fixes, for instance, object highlighting in Diablo 3 (wine).
* nvc0/ir: TEX doesn't support JOIN modifier eitherChristoph Bumiller2012-05-291-0/+1
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* nv30: Fix generic passing to fragment program in NV34.Roy Spliet2012-05-253-5/+9
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* nv30: handle user index buffersChristoph Bumiller2012-05-254-17/+27
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* radeon/llvm: Use a custom inserter for MASK_WRITETom Stellard2012-05-254-34/+36
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* radeon/llvm: Use tablegen pattern to lower bitconvertTom Stellard2012-05-254-294/+11
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* radeon/llvm: Use a custom inserter to lower FNEGTom Stellard2012-05-255-22/+15
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* radeon/llvm: Use a custom inserter to lower CLAMPTom Stellard2012-05-259-84/+41
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* radeon/llvm: Use a custom inserter to lower FABSTom Stellard2012-05-2510-42/+41
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* r600g: handle R16G16B16_FLOAT and R32G32B32_FLOAT in translate_colorswapKai Wasserbäch2012-05-251-0/+2
| | | | | | Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50318 Signed-off-by: Kai Wasserbäch <[email protected]>
* svga: remove the special zero-stride vertex array codeBrian Paul2012-05-259-153/+12
| | | | | This code actually hasn't been needed for some time now. We can just treat a zero-stride vertex array like any other non-zero-stride array.
* Revert "r600g: set round_mode to truncate and get rid of tgsi_f2i on evergreen"Vadim Girlin2012-05-252-6/+56
| | | | | | | | | | | | This reverts commit 60bf0f05b472e66bf1175fcec7a274dab6f7e2a3. It seems round_mode behaves differently in some cases depending on the instruction/slot. Reverting it for now. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50232 Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: add FLT_TO_UINT, UINT_TO_FLT instructionsVadim Girlin2012-05-251-0/+20
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: prepare to revert the round mode state to defaultVadim Girlin2012-05-251-2/+9
| | | | | | | Use TRUNC before FLT_TO_INT on evergreen/cayman. Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: fix sampler index in llvm_emit_texVadim Girlin2012-05-251-2/+4
| | | | | | | | | | Sampler index isn't a second source operand for some tgsi texture instructions. Let's assume it's always the last. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50230 Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: fix opcode for RECIP_UINT_r600Vadim Girlin2012-05-251-1/+1
| | | | | | | | Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50312 Signed-off-by: Vadim Girlin <[email protected]> Tested-by: Kai Wasserbäch <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm/loader: convert hardcoded gpu name to optionVadim Girlin2012-05-251-2/+3
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g: add RECIP_INT, PRED_SETE_INT to r600_bytecode_get_num_operandsVadim Girlin2012-05-251-0/+2
| | | | | | | | Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50315 Signed-off-by: Vadim Girlin <[email protected]> Tested-by: Kai Wasserbäch <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* i915g: Check for geometry shader earlier in i915_set_constant_buffer.Vinson Lee2012-05-241-4/+4
| | | | | | | Fix resource leak defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radeon/llvm: Lower UDIV using the Selection DAGTom Stellard2012-05-248-212/+126
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* radeon/llvm: Remove auto-generated AMDIL->ISA conversion codeTom Stellard2012-05-2414-280/+28
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* radeon/llvm: Remove AMDIL instructions MULHI, SMULTom Stellard2012-05-243-10/+5
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* radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR)Tom Stellard2012-05-248-693/+6
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* radeon/llvm: Remove AMDIL FTOI and ITOF instructionsTom Stellard2012-05-247-316/+7
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* radeon/llvm: Remove AMDIL EXP* instructionsTom Stellard2012-05-245-15/+7
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* radeon/llvm: Remove AMDIL ADD instructionsTom Stellard2012-05-246-179/+4
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* radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT)Tom Stellard2012-05-248-422/+8
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* radeon/llvm: Remove AMDILMachinePeephole passTom Stellard2012-05-244-177/+0
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* radeon/llvm: Remove AMDIL CMP instructions and associated lowering codeTom Stellard2012-05-243-661/+22
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* radeon/llvm: Remove AMDIL ROUND_NEAREST instructionTom Stellard2012-05-244-6/+6
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* radeon/llvm: Remove AMDIL ROUND_POSINF instructionTom Stellard2012-05-244-6/+10
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* radeon/llvm: Add custom SDNode for FRACTTom Stellard2012-05-246-6/+10
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* radeon/llvm: Use -1 as true value for SET* integer instructionsTom Stellard2012-05-243-32/+28
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* radeon/llvm: Handle SETGE_INT, SETGE_UINT, and SETGT_UINT opcodesTom Stellard2012-05-241-0/+6
| | | | | Support for these was inadvertently dropped in commit cee23ab246f22210b3063cdc47bdb45b3d943526
* radeon/llvm: Avoid error with SI in EmitInstrWithCustomInserter()Tom Stellard2012-05-241-0/+1
| | | | | | We need to return immediately after inserting instructions that require S_WAITCNT so that the parent class' custom inserter won't try to insert them again.
* llvmpipe: Fix alpha testing precision on rgba8 formats.José Fonseca2012-05-223-1/+34
| | | | | | | | | | This is a long standing problem, that recently surfaced with the change to enable perspective correct color interpolation. A fix for all possible formats is left to the future. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* nv30: check for NULL vertex buffers in prevalidate_vbufsChristoph Bumiller2012-05-221-1/+1
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* nv50: make unaligned index buffer offsets work againChristoph Bumiller2012-05-221-1/+3
| | | | Messed up in ef7bb281292c17b762b57779306e874704c87328.
* nvc0: don't set NEW_IDXBUF in nvc0_switch_pipe_context if none is boundChristoph Bumiller2012-05-221-0/+2
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* llvmpipe: Added a error counter to lp_test_conv.James Benton2012-05-211-3/+7
| | | | | | Useful for keeping track of progress when fixing errors! Signed-off-by: José Fonseca <[email protected]>
* llvmpipe: Changed known failures in lp_test_conv.James Benton2012-05-211-3/+9
| | | | | | To comply with the recent fixes to lp_bld_conv. Signed-off-by: José Fonseca <[email protected]>
* llvmpipe: Added fixed point types tests to lp_test_conv.James Benton2012-05-211-6/+7
| | | | Signed-off-by: José Fonseca <[email protected]>
* radeon/llvm: Handle selectcc DAG nodeTom Stellard2012-05-207-54/+350
| | | | | R600 can now select instructions from the selectcc DAG node, which is typically lowered to one of the SET* instructions.
* svga: whitespace, comments, formatting clean-upsBrian Paul2012-05-191-38/+31
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* svga: return PIPE_OK instead of 0Brian Paul2012-05-195-11/+11
| | | | And fix the emit_rss() function's return type.
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