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* trace: Support geometry shaders.José Fonseca2012-11-091-115/+71
| | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* galahad: Support geometry shader / stream-output methods.José Fonseca2012-11-091-82/+110
| | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* softpipe: Fix rgb_dst_factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE.José Fonseca2012-11-091-3/+3
| | | | | | | | | We must multiply the factor against the destination, not the source. NOTE: Candidate for the stable branches. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* softpipe: Handle adjacency primitives.José Fonseca2012-11-091-0/+46
| | | | | | | | | | | | Not fully tested. Based on diagrams from http://msdn.microsoft.com/en-us/library/windows/desktop/bb205124.aspx#Primitive_Adjacency v2: Fix based on Brian's feedback. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* svga: Fix memory leak in svga_buffer_transfer_map.Vinson Lee2012-11-081-0/+2
| | | | | | | Fixes resource leak defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* softpipe: add ARB_texture_cube_map_array support (v1.1)Dave Airlie2012-11-094-14/+171
| | | | | | | | | | | | | This adds support to the softpipe texture sampler and tgsi exec. In order to handle the extra input to the texture sampling, I've had to expand the interfaces to take a c1 value for storing the texture compare value for the TEX2 case. v1.1: add comments (Brian) Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix lod bias/explicit lod with cube maps.Dave Airlie2012-11-091-8/+20
| | | | | | | | | | | | While developing cube map array support I found that we didn't support this properly, also piglit didn't test for it at all. I've submitted a test to piglit to check for this, and this fixes explicit lod and lod bias with cube maps. NOTE: This is a candidate for the 9.0 branch. Signed-off-by: Dave Airlie <[email protected]>
* r600g: clarify const buffer numbering and handlingDave Airlie2012-11-094-4/+10
| | | | | | | | | For cube map arrays I'll need another driver private constant buffer, and looking forward to UBOs. So clean up with some defines, that can be modified when adding cube map array and ubos later. Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix pre eg export with llvmVincent Lejeune2012-11-081-1/+1
| | | | | Reviewed-by: Alex Deucher <alexander.deucher at amd.com> Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
* r600g/compute: fix call to r600_bytecode_initAlex Deucher2012-11-071-1/+2
| | | | Signed-off-by: Alex Deucher <[email protected]>
* svga: Ensure vb_transfer in svga_swtnl_draw_vbo in initialized.Vinson Lee2012-11-061-1/+1
| | | | | | | Fixes a uninitialized pointer read defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* r600g: add in-place DB decompression and texturing with DB tilingMarek Olšák2012-11-068-79/+216
| | | | | | | | | | | | | | | | | | | | | The decompression is done in-place and only the compressed tiles are decompressed. Note: R6xx-R7xx can do that only with Z16 and Z32F. The texture unit is programmed to use non-displayable tiling and depth ordering of samples, so that it can fetch the texture in the native DB format. The latest version of the libdrm surface allocator is required for stencil texturing to work. The old one didn't create the mipmap tree correctly. We need a separate mipmap tree for stencil, because the stencil mipmap offsets are not really depth offsets/4. There are still some known bugs, but this should save some memory and it also improves performance a little bit in Lightsmark (especially with low resolutions; tested with Radeon HD 5000). The DB->CB copy is still used for transfers. Reviewed-by: Jerome Glisse <[email protected]>
* trace: Prevent segfault when passing NULL to set_vertex_buffers.José Fonseca2012-11-052-15/+23
| | | | State tracker now passes NULL buffer array to unbind buffers.
* galahad: Prevent segfault when passing NULL to set_vertex_buffers.José Fonseca2012-11-051-1/+1
| | | | State tracker now passes NULL buffer array to unbind buffers.
* nv50,nvc0: expose ARB_map_buffer_alignmentLucas Stach2012-11-044-6/+8
| | | | | | All HW buffers (also suballocated ones) are already aligned. Just make sure that also the initial sysram buffers have proper alignment.
* r600g: make tgsi-to-llvm generates store.pixel* intrinsic for fsVincent Lejeune2012-11-026-12/+130
| | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
* radeonsi: Implement support for vertex shader samplers.Michel Dänzer2012-11-022-22/+60
| | | | Signed-off-by: Michel Dänzer <[email protected]>
* r600g: re-enable handling of DISCARD_RANGE, improving performanceMarek Olšák2012-11-011-2/+0
| | | | | | It seems to work for me now. Even the graphics corruption is gone. This also boosts performance in Reaction Quake.
* r600g: fix abysmal performance in Reaction QuakeMarek Olšák2012-11-012-21/+24
| | | | | | | | | | | | | The problem was we set VRAM|GTT for relocations of STATIC resources. Setting just VRAM increases the framerate 4 times on my machine. I rewrote the switch statement and adjusted the domains for window framebuffers too. NOTE: This is a candidate for the stable branches. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Jerome Glisse <[email protected]>
* llvmpipe: Obey back writemask.José Fonseca2012-10-311-2/+8
| | | | | | | | Tested with a modified glean tstencil2 test. NOTE: This is a candidate for stable branches. Reviewed-by: Brian Paul <[email protected]>
* r600g: avoid shader needing too many gpr to lockup the gpu v2Jerome Glisse2012-10-313-34/+62
| | | | | | | | | | | | | | On r6xx/r7xx shader resource management need to make sure that the shader does not goes over the gpr register limit. Each specific asic has a maxmimum register that can be split btw shader stage. For each stage the shader must not use more register than the limit programmed. v2: Print an error message when discarding draw. Don't add another boolean to context structure, but rather propagate the discard boolean through the call chain. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: use SQ_VTX_SEMANTIC_CLEAR to clear the semantic registersMarek Olšák2012-10-314-99/+11
| | | | Reviewed-by: Alex Deucher <[email protected]>
* gallium: expose ARB_map_buffer_alignment on RadeonMarek Olšák2012-10-3111-2/+18
| | | | | | | | Reviewed-by: Brian Paul <[email protected]> v2: update relnotes-9.1 v3: use align_malloc and align_free for malloced buffers in r300g v4: document the new CAP in the docs
* r600g: use better sample positions for 8x MSAAMarek Olšák2012-10-312-12/+12
| | | | | Taken from the intel driver. The sample positions are actually a solution to the 8 queens puzzle. It gives more accurate and smoother AA.
* gallium: add start_slot parameter to set_vertex_buffersMarek Olšák2012-10-3130-183/+158
| | | | | | | | | | | | | | | | | | | | | This allows updating only a subrange of buffer bindings. set_vertex_buffers(pipe, start_slot, count, NULL) unbinds buffers in that range. Binding NULL resources unbinds buffers too (both buffer and user_buffer must be NULL). The meta ops are adapted to only save, change, and restore the single slot they use. The cso_context can save and restore only one vertex buffer slot. The clients can query which one it is using cso_get_aux_vertex_buffer_slot. It's currently set to 0. (the Draw module breaks if it's set to non-zero) It should decrease the CPU overhead when using a lot of meta ops, but the drivers must be able to treat each vertex buffer slot as a separate state (only r600g does so at the moment). I can imagine this also being useful for optimizing some OpenGL use cases. Reviewed-by: Brian Paul <[email protected]>
* r600g: tgsi-to-llvm emits right input intrinsicsVincent Lejeune2012-10-302-20/+64
| | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
* r600g: implement texturing with 8x MSAA compressed surfaces for EvergreenMarek Olšák2012-10-2911-37/+256
| | | | | | | | | | The 2x and 4x MSAA cases are completely broken. The lfdptr instruction returns garbage there. The 8x MSAA case is broken on Cayman, though at least the result looks somewhat correct. Only the 8x MSAA case works on Evergreen and is enabled.
* nv50/ir: restore use of long immediate encodingsChristoph Bumiller2012-10-282-0/+9
| | | | NOTE: This is a candidate for the 9.0 branch.
* nv50,nvc0: fix 2d engine stencil-only copiesChristoph Bumiller2012-10-284-22/+48
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* r600g: advertise 32 streamout vec4 outputsMarek Olšák2012-10-261-1/+1
| | | | to match the varying limit.
* softpipe: remove extraneous whitespaceBrian Paul2012-10-261-2/+0
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* gallivm/llvmpipe: fix 64-bit %ll format compiler warnings for mingw32Brian Paul2012-10-261-4/+7
| | | | | Use the PRIx64 and PRIu64 format macros from inttypes.h. We made a similar change in prog_print.c in df2d81ea59993a77bd1f1ef96c5cf19ac692d5f7.
* r600g: advertise 32 fragment shaders inputs, not 34Marek Olšák2012-10-261-4/+1
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* trace: Flush before drawing.José Fonseca2012-10-263-0/+11
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* radeonsi: Handle TGSI_SEMANTIC_FACE.Michel Dänzer2012-10-262-1/+31
| | | | | | | Fixes two piglit tests using gl_FrontFacing. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: Handle TGSI_SEMANTIC_BCOLOR.Michel Dänzer2012-10-265-15/+75
| | | | | | | | | | Put the back face colour right after the front face colour in the LDS parameter space. Fixes 18 piglit tests related to two sided lighting. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: Don't snoop context state while building shaders.Michel Dänzer2012-10-263-17/+27
| | | | | | | | | Let's use the shader key describing the state. Ported from r600g commit b6521801070d52bdd5908824e82c1ce2dde16e8e. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Add intrinsic for reading SI FRONT_FACE VGPR in the pixel shader.Michel Dänzer2012-10-262-0/+6
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g: split cayman common state out into a shared functionAlex Deucher2012-10-263-16/+35
| | | | | | | | | And use it for compute. This should improve compute support on cayman. Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g: emit some additional regs on caymanAlex Deucher2012-10-261-0/+54
| | | | | | | | | These are common to both evergreen and cayman, but were not emitted on cayman. Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g: there are 16 const buffer size regs for each shader stageAlex Deucher2012-10-261-2/+19
| | | | | | | | we were previously only setting 8 of them. Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g: rework evergreen_init_common_regs()Alex Deucher2012-10-261-40/+33
| | | | | | | | | Move gfx specific bits out as the code is shared with compute. Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g/compute: always CONTEXT_CONTROL packet at start of CSAlex Deucher2012-10-262-0/+10
| | | | | | | | | | It's required. The CP uses this to properly allocate new contexts. Also do a CS partial flush since we are updating CONFIG regs which are single state. Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r300g: fix texture border color for sRGB formatsMarek Olšák2012-10-261-4/+18
| | | | NOTE: This is a candidate for the stable branches.
* trace: Fix dumping of set_constant_buffer method.José Fonseca2012-10-253-9/+21
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* r600g: force bank_swizzle if already setVincent Lejeune2012-10-242-0/+4
| | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
* r600g: rewrite tgsi-to-llvm load-input to handle fragcoordVincent Lejeune2012-10-242-42/+84
| | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
* nv50/ir/tgsi: fix srcMask for TXP with SHADOW1DChristoph Bumiller2012-10-241-1/+1
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* r600g: Remove special handling of PRED_SET* insructions for LLVM 3.2Tom Stellard2012-10-191-0/+2
| | | | | The 3.2 version of the backend now sets all the correct fields for PRED_SET* instructions.
* radeon/llvm: Sort tgsi opcode action initializationTom Stellard2012-10-191-59/+50
| | | | This was done in order to identify and remove duplicate entries.
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