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* gallium: Replace u_simple_list.h with util/simple_list.hEric Anholt2015-01-2817-22/+17
| | | | | | | The code was exactly the same, except util/ has c++ guards and a struct simple_node declaration. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Enable VGPR spilling for all shader types v5Tom Stellard2015-01-288-52/+217
| | | | | | | | | | | | | | | | | | | | v2: - Only emit write SPI_TMPRING_SIZE once per packet. - Use context global scratch buffer. v3: - Patch shaders using WRITE_DATA packet instead of map/unmap. - Emit ICACHE_FLUSH, CS_PARTIAL_FLUSH, PS_PARTIAL_FLUSH, and VS_PARTIAL_FLUSH when patching shaders. v4: - Code cleanups. - Remove unnecessary multiplies. v5: - Patch shaders in system memory and re-upload to vram. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi/compute: Allocate the scratch buffer during state creationTom Stellard2015-01-282-24/+62
| | | | | | | | | | This moves scratch buffer allocation from si_launch_grid() to si_create_compute_state(). This helps to reduce the overhead of launching a kernel and also fixes a bug in the code that would cause the scratch buffer to be too small if a kernel with smaller scratch size was launched before a kernel with a larger scratch size. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Add radeon_shader_binary member to struct si_shaderTom Stellard2015-01-282-6/+6
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi/compute: Rename si_compute::program to si_compute::shaderTom Stellard2015-01-281-5/+5
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Avoid leaking memory when rebuilding shader statesMarek Olšák2015-01-283-4/+13
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r600g: add support for primitive id without geom shader (v2)Dave Airlie2015-01-286-1/+51
| | | | | | | | | | | | | | | | | | | GLSL 1.50 specifies a fragment shader may have a primitive id input without a geometry shader present. On r600 hw there is a special GS scenario for this, you have to enable GS_SCENARIO_A and pass the primitive id through the vertex shader which operates in GS_A mode. This is a first pass attempt at this, and passes the piglit tests that test for this. v1.1: clean up debug print + no need to assign key value to setup output. v2: add r600 support Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: move selecting the pixel shader earlier.Dave Airlie2015-01-281-3/+4
| | | | | | | | | | | In order to detect that a pixel shader has a prim id input when we have no geometry shader we need to reorder the shader selection so the pixel shader is selected first, then the vertex shader key can take into account the primitive id input requirement and lack of geom shader. Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g,radeonsi: Fix calculation of IR target cap string buffer sizeMichel Dänzer2015-01-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes writing beyond the allocated buffer: ==31855== Invalid write of size 1 ==31855== at 0x50AB2A9: vsprintf (iovsprintf.c:43) ==31855== by 0x508F6F6: sprintf (sprintf.c:32) ==31855== by 0xB59C7EC: r600_get_compute_param (r600_pipe_common.c:526) ==31855== by 0x5B2B7DE: get_compute_param<char> (device.cpp:37) ==31855== by 0x5B2B7DE: clover::device::ir_target() const (device.cpp:201) ==31855== by 0x5B398E0: clover::program::build(clover::ref_vector<clover::device> const&, char const*, clover::compat::vector<clover::compat::pair<clover::compat::string, clover::compat::string> > const&) (program.cpp:63) ==31855== by 0x5B20152: clBuildProgram (program.cpp:182) ==31855== by 0x400F41: main (hello_world.c:109) ==31855== Address 0x56fed5f is 0 bytes after a block of size 15 alloc'd ==31855== at 0x4C29180: operator new(unsigned long) (vg_replace_malloc.c:324) ==31855== by 0x5B2B7C2: allocate (new_allocator.h:104) ==31855== by 0x5B2B7C2: allocate (alloc_traits.h:357) ==31855== by 0x5B2B7C2: _M_allocate (stl_vector.h:170) ==31855== by 0x5B2B7C2: _M_create_storage (stl_vector.h:185) ==31855== by 0x5B2B7C2: _Vector_base (stl_vector.h:136) ==31855== by 0x5B2B7C2: vector (stl_vector.h:278) ==31855== by 0x5B2B7C2: get_compute_param<char> (device.cpp:35) ==31855== by 0x5B2B7C2: clover::device::ir_target() const (device.cpp:201) ==31855== by 0x5B398E0: clover::program::build(clover::ref_vector<clover::device> const&, char const*, clover::compat::vector<clover::compat::pair<clover::compat::string, clover::compat::string> > const&) (program.cpp:63) ==31855== by 0x5B20152: clBuildProgram (program.cpp:182) ==31855== by 0x400F41: main (hello_world.c:109) Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* vc4: Fix build since 8ed5305d28d9309d651dfec3fbf4349854694694Eric Anholt2015-01-201-1/+1
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* freedreno/a4xx: sysmem bypassRob Clark2015-01-201-3/+58
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2015-01-205-23/+36
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeonsi: Re-enable LLVM IR dumpsTom Stellard2015-01-201-1/+3
| | | | | This was inadvertently disabled by 761e36b4caab4e8e09a4c2b1409a825902fc7d2c.
* radeonsi/compute: Use relocs for scratch pointer rather than user sgprs v2Tom Stellard2015-01-201-0/+42
| | | | | | | | | Instead of passing a pointer to the scratch buffer via user sgprs, we now patch the shader with the buffer address using reloc information from the LLVM generated ELF. v2: - Make sure not to break older LLVM.
* radeon: Teach radeon_elf_read() how to parse reloc information v3Tom Stellard2015-01-205-7/+78
| | | | | | | | | v2: - Use strdup for copying reloc names. - Free reloc memory. v3: - Add free_relocs parameter to radeon_shader_binary_free_members()
* radeon: Add a helper function for freeing members of radeon_shader_binaryTom Stellard2015-01-204-6/+13
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* vc4: Add some dumping for STORE_TILE_BUFFER_GENERAL.Eric Anholt2015-01-151-1/+79
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* vc4: Add dumping for the TILE_RENDERING_MODE_CONFIG packet.Eric Anholt2015-01-151-1/+70
| | | | I wanted to read it, so I wrote parsing.
* vc4: Fix CL dumping trying to dump too far.Eric Anholt2015-01-151-2/+2
| | | | | Execution will end at the cl->next, because that's what ct0ea/ct1ea get programmed to.
* vc4: Fix texture type masking.Eric Anholt2015-01-151-1/+1
| | | | | Everything from ETC1 to RGBA64 was getting its top bit dropped, but we didn't use any of those formats.
* vc4: Colormask should apply after all other fragment ops (like logic op).Eric Anholt2015-01-151-9/+18
| | | | | Theoretically it should apply after dithering as well, but ditehring for 565 happens in fixed function in the TLB store.
* vc4: No turning unpack arguments into small immediates.Eric Anholt2015-01-151-0/+3
| | | | | Since unpack only happens on things read from the A register file, we have to leave them as something that can be allocated to A (temp or uniform).
* vc4: Move the tests for src needing to be an A register to vc4_qir.c.Eric Anholt2015-01-153-17/+28
| | | | I want it from another location.
* vc4: Don't swap the raddr on instructions doing unpacks.Eric Anholt2015-01-151-0/+5
| | | | | It would mean different unpacking behavior, since only the A file does unpack (with PM==0).
* vc4: Don't let pairing happen with badly mismatched unpack flags.Eric Anholt2015-01-151-0/+39
| | | | | No difference on shader-db, but prevents definite regressions in the blending changes.
* vc4: Don't let pairing happen with badly mismatched pack flags.Eric Anholt2015-01-151-0/+39
| | | | | No difference on shader-db, but will become more important as I introduce more use of pack flags with the blending changes.
* vc4: Fix early Z behavior on hardware.Eric Anholt2015-01-151-2/+1
| | | | | | It turns out the simulator was not treating this bit the same as the RPi, and I'd forgotten to remove it when turning on early Z. The result was that you'd get big chunks of your rendering missing.
* Revert "radeonsi: only set BC_OPTIMIZE_DISABLE when necessary"Michel Dänzer2015-01-152-15/+6
| | | | | | | | | | | | | | | | This reverts commit 0543630d0b0d9d9f6eefbc14fbd3385d4de37ba0. It caused flickering artifacts in Steam games such as Team Fortress 2 or Left 4 Dead 2. We could probably only enable this optimization by also making sure the shader code only uses either SI_PARAM_LINEAR_CENTROID or SI_PARAM_LINEAR_CENTER, not both. This would probably require a shader variant. Sorry I didn't remember this when reviewing the reverted change. Reviewed-by: Marek Olšák <[email protected]>
* freedreno/ir3: handle "holes" in inputsRob Clark2015-01-131-1/+31
| | | | | | | | | | | | If, for example, only the x/y/w components of in.xyzw are actually used, we still need to have a group of four registers and assign all four components. The hardware can't write in.xy and in.w to discontiguous registers. To handle this, pad with a dummy NOP instruction, to keep the neighbor chain contiguous. This fixes a problem noticed with firefox OMTC. Signed-off-by: Rob Clark <[email protected]>
* r600g: fix build failure when building the driver without LLVMMarek Olšák2015-01-121-0/+4
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* vc4: Clamp the inputs to the blend equation to [0, 1].Eric Anholt2015-01-111-1/+10
| | | | Fixes the remaining ARB_color_buffer_float rendering tests.
* vc4: Add a little helper for clamping to [0,1].Eric Anholt2015-01-111-4/+10
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* vc4: Fix up statechange management for uncompiled/compiled FS/VS.Eric Anholt2015-01-112-11/+10
| | | | | | | | No need to recheck the FS compile when the VS source has changed, but there *is* a need to recheck the VS compile when the compiled VS has changed (since the live inputs may change). Fixes es3conform's blend test.
* vc4: Fix clear color setup for RGB565.Eric Anholt2015-01-111-1/+4
| | | | | | | The util_pack_color() thing only sets up the low bits of the union, so only return them, too. Fixes intermittent failure on fbo-alphatest-formats and es3conform's framebuffer-objects test under simulation.
* vc4: Avoid the save/restore of r3 for raddr conflicts, just use ra31.Eric Anholt2015-01-112-38/+11
| | | | | | | | | | | | | Turns out this was harmful in code quality: total instructions in shared programs: 39487 -> 38845 (-1.63%) instructions in affected programs: 22522 -> 21880 (-2.85%) This costs us yet another register, which is painful since it means more programs might fail to compile). However, the alternative was causing us trouble where we'd save/restore r3 while it contained a MIN-ed direct texture offset, causing the kernel to fail to validate our shaders (such as in GLB2.7).
* vc4: Allow dead code elimination of VPM reads.Eric Anholt2015-01-102-1/+44
| | | | | | | | This gets a bunch of dead reads out of the CSes, which don't read most attributes generally. total instructions in shared programs: 39753 -> 39487 (-0.67%) instructions in affected programs: 4721 -> 4455 (-5.63%)
* vc4: Cook up the draw-time VPM setup info during shader compile.Eric Anholt2015-01-104-11/+28
| | | | | | This will give the compiler the chance to dead-code eliminate unused VPM reads. This is particularly a big deal in the CS where a bunch of vattrs are just not going to be used.
* vc4: Split two notions of instructions having side effects.Eric Anholt2015-01-105-4/+15
| | | | | Some ops can't be DCEd, while some of the ops that are just important due to the args they have can be.
* vc4: Redo VPM reads as a read file.Eric Anholt2015-01-105-16/+16
| | | | This will let us do copy propagation of the VPM reads.
* vc4: Fix miscalculation of the VPM space.Eric Anholt2015-01-101-1/+1
| | | | | We pass in a byte offset, not dword. I'm rather scared that this actually managed to pass piglit, but it does fix gears.
* vc4: Pack VPM attr contents according to just the size of the attribute.Eric Anholt2015-01-103-11/+9
| | | | | total instructions in shared programs: 40960 -> 39753 (-2.95%) instructions in affected programs: 20871 -> 19664 (-5.78%)
* vc4: Restructure color packing as a series of channel replacements.Eric Anholt2015-01-104-49/+60
| | | | | | | | | I'm using this in some WIP commits for doing blending in 8888 instead of vec4. But it also gives us these results immediately, thanks to allowing more uniforms/immediates in the arguments: total instructions in shared programs: 41027 -> 40960 (-0.16%) instructions in affected programs: 4381 -> 4314 (-1.53%)
* vc4: Fix the no-copy-propagating-from-TLB_COLOR_READ check.Eric Anholt2015-01-101-1/+1
| | | | | Our MOV's dst obviously won't be the TLB_COLOR_READ's def, because we're ssa.
* vc4: Move global seqno short-circuiting to vc4_wait_seqno().Eric Anholt2015-01-102-6/+3
| | | | Any other caller would want it, too.
* freedreno/ir3: fix pos_regid > max_regRob Clark2015-01-074-41/+121
| | | | | | | | | | | | | | We can't (or don't know how to) turn this off. But it can end up being stored to a higher reg # than what the shader uses, leading to corruption. Also we currently aren't clever enough to turn off frag_coord/frag_face if the input is dead-code, so just fixup max_reg/max_half_reg. Re-org this a bit so both vp and fp reg footprint fixup are called by a common fxn used also by ir3_cmdline. Also add a few more output lines for ir3_cmdline to make it easier to see what is going on. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: start on indirect gpr readsRob Clark2015-01-073-8/+146
| | | | | | | | | | | | | | Handle TEMP[ADDR[]] src registers by generating a fanin to group array elements, similarly to how texture fetch instructions work. NOTE: For all the scalar instructions generated for a single tgsi vector operation which uses an array src (or possibly even uses the same array as multiple srcs), re-use the same fanin node. Since a vector operation operates on all components at the same time, it should never see more than one version of the same array. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: make reg array dynamicRob Clark2015-01-074-13/+50
| | | | | | | | | To use fanin's to group registers in an array, we can potentially have a much larger array of registers. Rather than continuing to bump up the array size, just make it dynamically allocated when the instruction is created. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: simplify RARob Clark2015-01-078-777/+622
| | | | | | | | | | | | | | | | | | | | | | Group inputs/outputs, in addition to fanin/fanout, as they must also exist in sequential scalar registers. This lets us simplify RA by working in terms of neighbor groups. NOTE: has the slight problem that it can't optimize out mov's for things like: MOV OUT[n], IN[m] To avoid this, instead of trying to figure out what mov's we can eliminate, we first remove all mov's prior to grouping, and then re-insert mov's as needed while grouping inputs/outputs/fanins. Eventually we'd prefer the frontend to not insert extra mov's in the first place (so we don't have to bother removing them). This is the plan for an eventual NIR based frontend, so separate out the instr grouping (which will still be needed for NIR frontend) from the mov elimination (which won't). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: regmask support for relative addrRob Clark2015-01-072-17/+51
| | | | | | | | For temp arrays, a 32bit mask won't be sufficient.. but otoh we don't need to support an arbitrary mask. So for this case use a simple size field rather than a bitmask. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split up ssa_srcRob Clark2015-01-071-23/+34
| | | | | | | Slight bit of refactoring that will be needed for indirect gpr addressing (TEMP[ADDR[]]). Signed-off-by: Rob Clark <[email protected]>
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