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* r600g: adjust QUANT_MODE for higher precisionVadim Girlin2012-09-044-2/+24
| | | | | | | | | Use 1/256 for R6xx/7xx, 1/4096 for evergreen, instead of default 1/16. Helps to pass some piglit tests (fbo, multisample). Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: disable array-textures for nowChristian König2012-09-031-1/+1
| | | | Signed-off-by: Christian König <[email protected]>
* radeonsi: disable Z16 for nowChristian König2012-09-031-2/+2
| | | | | | | It's causing crashes. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: disable NPOT textures for nowChristian König2012-09-031-1/+1
| | | | | | | | | Looks like we have an alignment issue with NPOT textures and mipmaps. So disable NPOT textures until we figure out what is going wrong here. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: handle indirect constants gracefullyChristian König2012-09-031-0/+7
| | | | | | | It's not supported yet, so at least don't try to crash the box. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/llvm: Rework how immediate operands are handled with SITom Stellard2012-08-3110-44/+150
| | | | | | | Immediate operands were previously handled in the CodeEmitter, but that code was buggy and very confusing. This commit adds a pass that simplifies the handling of immediate operands by spliting the loading of the immediate into a sperate insruction that is bundled with the original.
* radeon/llvm: Fix typo in assertTom Stellard2012-08-311-1/+1
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* radeon/llvm: Fix isEG tablegen predicateTom Stellard2012-08-311-3/+5
| | | | | This predicate incorrectly included SI GPUs, so some Evergreen instructions were being emmitted on SI.
* radeon/llvm: Add support for RCP instruction on SITom Stellard2012-08-311-1/+3
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* radeon/llvm: Support AMDGPUfmin DAG node on SITom Stellard2012-08-311-1/+3
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* radeonsi: Handle TGSI_SEMANTIC_PSIZETom Stellard2012-08-311-0/+1
| | | | | | | | | | The relevant POINT_SIZE registers are being set using the pipe_rasterizer_state, so we just need to tell the shader compiler which export type to use. This fixes several of the glean glsl tests. Reviewed-by: Alex Deucher <[email protected]>
* r600g: enable transform feedback on CaymanMarek Olšák2012-08-311-3/+1
| | | | There doesn't seem to be anything wrong with it.
* r600g: implement MSAA for CaymanMarek Olšák2012-08-316-72/+184
| | | | | Everything works except for blitting MSAA colorbuffers, which isn't so trivial on Cayman. It's a rarely-used feature anyway.
* r600g: enable MSAA on r6xx by defaultMarek Olšák2012-08-301-3/+6
| | | | | DRM 2.22.0 is required though. Also require the new DRM for r700, as there are some important fixes for that generation too.
* r600g: disable MSAA depth decompression on r6xxMarek Olšák2012-08-301-1/+10
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* r600g: implement color resolve for r600Marek Olšák2012-08-307-26/+199
| | | | | | | | | The blend state is different and the resolve single-sample buffer must have FMASK and CMASK enabled. I decided to have one CMASK and one FMASK per context instead of per resource. There are new FMASK and CMASK allocation helpers and a new buffer_create helper for that.
* r600g: fix CB_SHADER_MASK and CB_TARGET_MASK for r6xxMarek Olšák2012-08-301-11/+24
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* r600g: implement draw_rectangle callbackMarek Olšák2012-08-303-2/+72
| | | | | | The color resolve on r6xx needs PT_RECTLIST. Using conventional primitive types (triangles and quads) produces an ugly line between two diagonally opposite corners. I guess a rectangular point sprite would work too.
* r600g: implement MSAA for r700Marek Olšák2012-08-307-41/+262
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: change programming of CB_SHADER_MASK on r600-r700Marek Olšák2012-08-301-1/+2
| | | | | | | This one actually makes more sense and gives the expected value for MSAA resolve. Reviewed-by: Jerome Glisse <[email protected]>
* radeonsi: fix stupid bug added in commit ↵Christian König2012-08-301-7/+8
| | | | | | | 07838603b9a69c05911edbcd351bfce5ad9b5a2c Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/llvm: Fix encoding of FP immediates on SITom Stellard2012-08-291-1/+6
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* radeon/llvm: Create a register class for the M0 registerTom Stellard2012-08-295-16/+24
| | | | | | | | | | | The Common Subexpression Elimination pass will not operate on instructions with physical register defs, so we end up with several redundant copies to M0 when using interpolation. Adding a register class that only contains the M0 register allows use to use a virtual register to represent M0, and makes it possible for the Common Subexpression Elimination pass to remove the extra copies.
* radeon/llvm: Set the neverHasSideEffects bit on more instructionsTom Stellard2012-08-291-0/+2
| | | | | This flag makes these instructions candidates for the dead code elimination and common subexpression elimination.
* radeon/llvm: Declare the interpolation intrinsics as ReadOnlyTom Stellard2012-08-293-3/+4
| | | | | This signals to the Dead Code Elimination pass that it is safe to remove these instructions when they are dead.
* radeon/llvm: Mark M0 as a def when lowering interpolation instructionsTom Stellard2012-08-291-4/+2
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* radeon/llvm: Handle TGSI KIL opcode for SI.Michel Dänzer2012-08-283-0/+44
| | | | | | | Fixes piglit fp-kil and glBitmap() with radeonsi. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Basic support for SI EXEC register.Michel Dänzer2012-08-283-2/+23
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: Don't write to the PA_SC_RASTER_CONFIG register.Michel Dänzer2012-08-281-1/+0
| | | | | | | It should be initialized by the kernel as necessary. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* r600g: fix relative addressing on RS780 and RS880Marek Olšák2012-08-281-7/+6
| | | | | | They should be treated like RV670. Tested-by: Michel Dänzer <[email protected]>
* llvmpipe: Bump the maximum texture size (in pixels).José Fonseca2012-08-282-2/+9
| | | | | | | | | | But cap the size in bytes, to avoid depleting the whole system memory, with humongus textures. Tested with max-texture-size piglit test. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* r300g: implement TRUNC correctlyMarek Olšák2012-08-274-1/+42
| | | | This fixes some integer division tests.
* radeonsi: Use FP16 shader export format when necessary / possible.Michel Dänzer2012-08-276-18/+114
| | | | | | | | | Fixes piglit fbo-blending-formats. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Refactor initialization of shader export intrinsic arguments.Michel Dänzer2012-08-271-36/+48
| | | | | | | | | In preparation for extending this code, which would make it rather unwieldy in its current place. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Maintain cache of pixel shader variants according to contxt state.Michel Dänzer2012-08-276-59/+210
| | | | | | | | | Mostly inspired by r600g commit 4acf71f01ea1edb253cd38cc059d4af1a2a40bf4 ('r600g: cache shader variants instead of rebuilding v3'). Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Drop extraneous semicolons from pm4 state macro definitions.Michel Dänzer2012-08-271-3/+3
| | | | | | | | Could cause build failures if trying to use the macros in certain constructs. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: implement compression for MSAA colorbuffers for evergreenMarek Olšák2012-08-2710-19/+479
| | | | | | | | | | | | | | | | This adds the FMASK and CMASK buffers. They share the same resource with color data. COMPRESSION and FAST_CLEAR are always enabled if both FMASK and CMASK are allocated. We initialize the CMASK to a "compressed" state (not "fast cleared"), so that we can keep FAST_CLEAR enabled all the time. Both FMASK and CMASK must be present at the moment. If either one is missing, the other one is not used. v2: add cayman regs in the list Reviewed-by: Jerome Glisse <[email protected]>
* r600g: cleanup names around depth decompressionMarek Olšák2012-08-275-24/+24
| | | | | | for consistency with the upcoming color decompression naming Reviewed-by: Jerome Glisse <[email protected]>
* r600g: fix evergreen 8x MSAA sample positionsMarek Olšák2012-08-271-16/+16
| | | | | | | The original samples positions took samples outside of the pixel boundary, leading to dark pixels on the edge of the colorbuffer, among other things. Reviewed-by: Jerome Glisse <[email protected]>
* r600g: set CB_TARGET_MASK to 0xf and not 0xff for resolve on evergreenMarek Olšák2012-08-271-0/+1
| | | | | | | independent_blend_enable must be true, so that the colormask isn't replicated in all colorbuffers. Reviewed-by: Jerome Glisse <[email protected]>
* r300/compiler: Use variable lists in the rename_regs passTom Stellard2012-08-261-17/+14
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* radeonsi: remove old tilling handlingChristian König2012-08-243-279/+31
| | | | | | | | | Just use the functionality provided by the surface manager instead. This fixes just another bunch of piglit tests. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Cleanup R600Instructions.tdTom Stellard2012-08-242-93/+28
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* radeon/llvm: Set End of Program bit on RAT instructionsTom Stellard2012-08-233-10/+14
| | | | This code was accidently dropped during the MCCodeEmitter conversion.
* radeon/llvm: Use correct instruction for moving immediatesTom Stellard2012-08-231-1/+2
| | | | | This should fix an assertion failure that was happening in some compute shaders.
* radeon/llvm: Fix some coding style issuesTom Stellard2012-08-2314-82/+135
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* radeon/llvm: Pull changes from external version of the backendTom Stellard2012-08-2321-76/+38
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* radeon/llvm: Simplify the convert to ISA passTom Stellard2012-08-233-20/+7
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* radeon/llvm: Make sure to use the Text section in the AsmPrinterTom Stellard2012-08-231-0/+2
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* radeon/llvm: Use the MCCodeEmitter for R600Tom Stellard2012-08-2316-738/+779
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