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* ilo: define ILO_IMAGE_MAX_LEVEL_COUNTChia-I Wu2015-06-264-8/+16
| | | | | Define ILO_IMAGE_MAX_LEVEL_COUNT for ilo_image and remove unnecessary header includes.
* ilo: replace pipe_format by gen_surface_formatChia-I Wu2015-06-2613-142/+174
| | | | | Replace pipe_format by gen_surface_format in ilo_image. Change how depth format is specified in ilo_state_zs.
* ilo: always use the specified image formatChia-I Wu2015-06-264-69/+115
| | | | | Move silent promotion of PIPE_FORMAT_ETC1_RGB8 or combined depth/stencil out of core.
* ilo: replace pipe_texture_target by gen_surface_typeChia-I Wu2015-06-268-125/+98
| | | | | Replace pipe_texture_target by gen_surface_type in ilo_image. Change how GEN6_SURFTYPE_CUBE is specified in ilo_state_surface and ilo_state_zs.
* ilo: initialize ilo_image from ilo_image_infoChia-I Wu2015-06-263-179/+242
| | | | Convert pipe_resource to ilo_image_info for image initialization.
* ilo: remove ilo_image_disable_aux()Chia-I Wu2015-06-263-28/+2
| | | | Fail resource creation when aux bo allocation fails.
* ilo: improve SURFTYPE_BUFFER validationsChia-I Wu2015-06-262-81/+139
| | | | Reorganize the validations to make them more systematic.
* ilo: remove ilo_bufferChia-I Wu2015-06-2610-68/+109
| | | | | | | | | | Since the addition of ilo_vma, it was used only to pad a bo for sampling engine surfaces. Replace it entirely with these functions ilo_state_surface_buffer_size() ilo_state_vertex_buffer_size() ilo_state_index_buffer_size() ilo_state_sol_buffer_size()
* ilo: introduce ilo_vmaChia-I Wu2015-06-2621-315/+419
| | | | | This cleans up the code a bit and makes ilo_state_vector_resource_renamed() simpler and more robust. It also allows a single bo to back mulitple VMAs.
* radeonsi: don't fail in si_shader_io_get_unique_indexMarek Olšák2015-06-251-2/+6
| | | | Trivial. Picked from my tessellation branch.
* svga: silence warnings about unexpected shader typeBrian Paul2015-06-241-1/+3
| | | | Trivial.
* vc4: Also dump VC4_PACKET_LOAD_TILE_BUFFER_GENERAL.Eric Anholt2015-06-231-2/+14
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* vc4: Add dumping for VC4_PACKET_LOAD/STORE_FULL_RES_TILE_BUFFER.Eric Anholt2015-06-232-2/+38
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* vc4: Don't try to CSE color reads.Eric Anholt2015-06-231-1/+2
| | | | | | It returns a new value for each sample in the TLB. We've already avoided trying to get the same index's color multiple times at the vc4_program.c level, so we're not losing anything by doing this.
* vc4: Make a helper for TLB color writes, too.Eric Anholt2015-06-232-1/+2
| | | | We've done so for all the other QIR instruction generation in this file.
* vc4: Pull the blending operation out to a separate function.Eric Anholt2015-06-231-38/+50
| | | | | It's fairly separate from the rest of the TLB operations at frag end time, and we'll need to run it multiple times to support MSAA blending.
* vc4: Clarify size calculation for Z/S writes.Eric Anholt2015-06-231-1/+1
| | | | | It's the same value for loads and stores, because they're basically the same packet.
* vc4: Add an "args" temporary for RCL setup.Eric Anholt2015-06-231-24/+24
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* vc4: Reuse (and extend) the packet.h sizes for dumping.Eric Anholt2015-06-232-51/+58
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* vc4: Fix printfs for blit fallbacks.Eric Anholt2015-06-231-3/+3
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* nv50,nvc0: make sure to pushbuf_refn before putting bo into pushbuf_dataIlia Mirkin2015-06-234-0/+4
| | | | | | | | | | | | Without first running the bo through pushbuf_refn, the nouveau drm library will have uninitialized structures regarding this bo, and will insert incorrect data. This fixes supertuxkart 0.9 crash on start (where it ends up doing a lot of indirect draws). Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* nvc0: always put all tfb bufs into bufctxIlia Mirkin2015-06-231-3/+4
| | | | | | | | | | Since we clear the TFB bufctx binding point above, we need to put all of the active tfb's back in, even if they haven't changed since last time. Otherwise the tfb may get moved into sysmem and the underlying mapping will generate write errors. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* ilo: emit 3DPRIMITIVE from gen6_3dprimitive_infoChia-I Wu2015-06-2211-87/+91
| | | | | | It allows us to remove ilo_ib_state::draw_start_offset and ILO_PRIM_RECTANGLES. gen6_3d_translate_pipe_prim() is also replaced by ilo_translate_draw_mode().
* ilo: align vertex buffer size in buf_create()Chia-I Wu2015-06-222-19/+20
| | | | | With ilo_format.[ch] moved out of core, the aligning of vertex buffers does not belong to core anymore.
* ilo: move ilo_format.[ch] out of coreChia-I Wu2015-06-225-8/+8
| | | | | They provide PIPE_FORMAT_x to GEN6_FORMAT_x translation as well as some convenient helpers. Move them out of core.
* ilo: add ilo_state_surface_valid_format()Chia-I Wu2015-06-224-284/+364
| | | | Check if a surface format can be used for the specified access type.
* ilo: add ilo_state_vf_valid_element_format()Chia-I Wu2015-06-223-124/+132
| | | | Check if a surface format can be used as a VE format.
* nvc0: use NV_VRAM_DOMAIN() macroAlexandre Courbot2015-06-2211-22/+27
| | | | | | | | | Use the newly-introduced NV_VRAM_DOMAIN() macro to support alternative VRAM domains for chips that do not have dedicated video memory. Signed-off-by: Alexandre Courbot <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* nouveau: support for custom VRAM domainsAlexandre Courbot2015-06-222-0/+14
| | | | | | | | | | | | | | | | | | | | | Some GPUs (e.g. GK20A, GM20B) do not embed VRAM of their own and use the system memory as a backend instead. For such systems, allocating objects in VRAM results in errors since the kernel will not allow VRAM objects allocations. This patch adds a vram_domain member to struct nouveau_screen that can optionally be initialized to an alternative domain to use for VRAM allocations. If left untouched, NOUVEAU_BO_VRAM will be used for systems that embed VRAM, and NOUVEAU_BO_GART will be used for VRAM-less systems. Code that uses GPU objects is then expected to use the NV_VRAM_DOMAIN() macro in place of NOUVEAU_BO_VRAM to ensure correct behavior on VRAM-less chips. Signed-off-by: Alexandre Courbot <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* ilo: add ilo_state_computeChia-I Wu2015-06-228-92/+586
| | | | | Replace gen6_idrt_data with ilo_state_compute, which has a bunch of validations and is now preferred.
* r600g: ignore sampler views for now.Dave Airlie2015-06-221-0/+1
| | | | | | | This fixes a regression in that r600 stopped working when sampler views were pushed. Signed-off-by: Dave Airlie <[email protected]>
* freedreno/ir3: pass sz to split_dest()Rob Clark2015-06-212-5/+7
| | | | | | | | | | | | | | | | | | | | For query_levels, we generate a getinfo with writemask of (z), which RA will consider as size==3. But we were still generating four fanouts. Which meant that RA would see it as two different register classes, depending on the path to definer. Ie. on the getinfo instruction itself it would see size==3, but when chasing back through the fanouts it would see size==4. Easiest way to solve that is to just generate the chain of neighboring fanouts to have the correct size in the first place. Note: we may eventually want split_dest() to take start/end or wrmask instead, since really we only need size==1. But RA is not clever enough for that, query_levels is not that common, and the other two registers that get allocated are never used so those register slots can be immediately re-used. So bunch of work for probably no real gain. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: add more opcodesRob Clark2015-06-211-1/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: only unminify txf coords on a3xxRob Clark2015-06-211-1/+9
| | | | | | Seems like a4xx gets this right. Signed-off-by: Rob Clark <[email protected]>
* freedreno: remove int sampler shader variantsRob Clark2015-06-218-104/+7
| | | | | | | | We get this information from NIR (which gets it from sview decl in tgsi when translating from tgsi), so no need to maintain shader variants for this. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: block reshuffling and loops!Rob Clark2015-06-2110-126/+1025
| | | | | | | | | | | | | | | | This shuffles things around to allow the shader to have multiple basic blocks. We drop the entire CFG structure from nir and just preserve the blocks. At scheduling we know whether to schedule conditional branches or unconditional jumps at the end of the block based on the # of block successors. (Dropping jumps to the following instruction, etc.) One slight complication is that variables (load_var/store_var, ie. arrays) are not in SSA form, so we have to figure out where to put the phi's ourself. For this, we use the predecessor set information from nir_block. (We could perhaps use NIR's dominance frontier information to help with this?) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: a4xx encodes larger immed offsetRob Clark2015-06-214-7/+21
| | | | | | | Without this, negative branch/jump offsets look like very large positive offsets. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: simplify find_neighbors stop conditionRob Clark2015-06-211-17/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move inputs/outputs to shaderRob Clark2015-06-2112-176/+160
| | | | | | | | | These belong in the shader, rather than the block. Mostly a lot of churn and nothing too interesting. But splitting this out from the rest of ir3_block reshuffling to cut down the noise in the later patch. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/ra: use register_allocateRob Clark2015-06-216-481/+590
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: introduce ir3_compiler objectRob Clark2015-06-2112-31/+90
| | | | | | | | Right now, just provides a cleaner way to get at the gpu-id, given the separation between compiler and context. But we will need this also to hold the reg-set for new register allocation. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: dump nocp optionRob Clark2015-06-213-8/+0
| | | | | | No longer used, or even possible, with NIR frontend. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: silence warningsRob Clark2015-06-211-1/+10
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove tgsi f/eRob Clark2015-06-2112-3957/+25
| | | | | | Also remove ir3_flatten which was only used by tgsi f/e. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/sched: convert to priority queueRob Clark2015-06-214-229/+242
| | | | | | | | Use a more standard priority-queue based scheduling algo. It is simpler and will make things easier once we have multiple basic blocks and flow control. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use standard list implementationRob Clark2015-06-218-209/+161
| | | | | | | | | | Use standard list_head double-linked list and related iterators, helpers, etc, rather than weird combo of instruction array and next pointers depending on stage. Now block has an instrs_list. In certain stages where we want to remove and re-add to the blocks list we just use list_replace() to copy the list to a new list_head. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: drop dot graph dumpingRob Clark2015-06-2110-525/+228
| | | | | | | | At least for now.. right now the instruction and instruction list printing should suffice, and the re-working of ir3_block would require a lot of changes in that code. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: more builder helpersRob Clark2015-06-214-21/+16
| | | | | | | | Use ir3_MOV() builder in a couple of spots, rather than open-coding the instruction construction. Also add ir3_NOP() builder and use that instead of open coding. Signed-off-by: Rob Clark <[email protected]>
* vc4: Use a defined t value for 1D textures.Eric Anholt2015-06-201-1/+3
| | | | | This doesn't fix the broken 1D cases of texsubimage, but it does prevent segfaulting when dumping the QIR code generated in fbo-1d.
* vc4: Fix write-only texsubimage when we had to align.Eric Anholt2015-06-201-1/+5
| | | | | | | | We need to make sure that when we store the aligned box, we've got initialized contents in the border. We could potentially just load the border area, but for now let's get text rendering working in X (and fix the GL_TEXTURE_2D errors in piglit's texsubimage test and gl-2.1-pbo/test_tex_image)
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