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* util: Move ralloc to a new src/util directory.Kenneth Graunke2014-08-042-1/+4
| | | | | | | | | | | | | | | | | | For a long time, we've wanted a place to put utility code which isn't directly tied to Mesa or Gallium internals. This patch creates a new src/util directory for exactly that purpose, and builds the contents as libmesautil.la. ralloc seemed like a good first candidate. These days, it's directly used by mesa/main, i965, i915, and r300g, so keeping it in src/glsl didn't make much sense. Signed-off-by: Kenneth Graunke <[email protected]> v2 (Jason Ekstrand): More realloc uses and some scons fixes Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* llvmpipe: don't store number of layers per levelRoland Scheidegger2014-08-012-78/+50
| | | | | | | | | | | | | | | | This could be recalculated, though it turns out the only use of it after resource allocation is for calculating whole resource size (for scene size accounting though that isn't quite ideal neither). Thus, instead just store the whole resource size and drop it (saving a couple bytes of storage per resource). It makes things simpler too. Note that for the accounting winsys resources always come back with size 0 but this is unchanged (we don't actually know the size in any case). Also reformat llvmpipe_texture_layout (drop unneded indentation). v2: adapt to previous changes. Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: integrate memory allocation into llvmpipe_texture_layoutRoland Scheidegger2014-08-011-45/+29
| | | | | | | | | | | | | | | Seems pointless to just duplicate some of the calculations (the calculation of actual memory used compared to what was predicted in llvmpipe_texture_layout actually could have differed slightly in some cases due to different alignment rules used though this should have been of no consequence). v2: keep the previous mip alignment of MAX2(64, cacheline). This was added for ARB_map_buffer_alignment - I'm not convinced it's needed for textures, but it was supposed to be cleanup without functional change. Also replace div with 64bit mul / comparison. Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: get rid of impossible code in alloc_image_dataRoland Scheidegger2014-08-011-26/+13
| | | | | | | Only used for non display target resources. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* r600g: Implement gpu_shader5 textureGatherGlenn Kennard2014-08-012-5/+36
| | | | | | | | | | | | | | | Adds 0-3 textureGather component selection and non-constant offsets Caveat: 0 and 1 texture swizzles only work if textureGather component select is 3 or a component that does not exist in the sampler texture format. This is a hardware limitation, any other value returns 128/255=0.501961 for both 0 and 1. Passes all textureGather piglit tests on radeon 6670, except for those using 0/1 texture swizzles due to aforementioned reason. Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* r600g/radeonsi: Prefer VRAM for CPU -> GPU streaming buffersMichel Dänzer2014-08-011-4/+11
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g/radeonsi: Reduce or even drop special treatment of persistent mappingsMichel Dänzer2014-08-011-4/+8
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g: gpu_shader5 gl_SampleMaskIn supportGlenn Kennard2014-07-312-7/+40
| | | | | | | | Map TGSI_SEMANTIC_SAMPLEMASK to register/component. Enable face register when sample mask is needed by shader. Requires Evergreen/Cayman Reviewed-by: Alex Deucher <[email protected]>
* r600g: Implement gpu_shader5 integer opsGlenn Kennard2014-07-311-0/+190
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: Add IMUL_HI/UMUL_HI supportGlenn Kennard2014-07-311-6/+6
| | | | | | | Fixes fs-imulExtended, fs-imulExtended-only-msb, fs-umulExtended, fs-umulExtended-only-msb piglit tests. Reviewed-by: Alex Deucher <[email protected]>
* r600g: Implement GL_ARB_texture_query_lodGlenn Kennard2014-07-312-2/+13
| | | | | | | | Requires Evergreen or later v2 (Andreas): Update relnotes/10.3 Reviewed-by: Alex Deucher <[email protected]> (v1)
* dri: Add a new capabilities for drivers that can't share buffersGiovanni Campagna2014-07-301-1/+1
| | | | | | | | | | | | | | | | | | | The kms-dri swrast driver cannot share buffers using the GEM, so it must tell the loader to disable extensions relying on that, without disabling the image DRI extension altogether (which would prevent the loader from working at all). This requires a new gallium capability (which is queried on the pipe_screen and for swrast drivers it's forwarded to the winsys), and requires a new version of the DRI image extension. [Emil Velikov] - Rebased on top of gallium-dri megadrivers. - Drop PIPE_CAP_BUFFER_SHARE and sw_winsys::get_param hook. The can_share_buffer cap is set at InitScreen. We use a different InitScreen (and thus value for the cap) function for kms_dri, due to deeper differences originating from dri megadrivers. Signed-off-by: Emil Velikov <[email protected]>
* svga: remove unneeded depth==1 assertion in svga_texture_view_surface()Brian Paul2014-07-291-1/+0
| | | | | | | We can create 3D texture views. Avoids an assertion in piglit fbo-generatemipmap-3d test and allows it to pass. Reviewed-by: Charmaine Lee <[email protected]>
* gallium/radeon: Add some Emacs .dir-locals.el filesMichel Dänzer2014-07-293-0/+33
| | | | | | Based on the toplevel one but adapted to the driver/winsys coding styles. Reviewed-by: Marek Olšák <[email protected]>
* ilo: fix fb height of HiZ opsChia-I Wu2014-07-291-1/+1
| | | | | It was set to aligned width. It appears to be fine on GEN7+, but causes random hangs on GEN6.
* r600g,radeonsi: switch all occurences of array_size to util_max_layerMarek Olšák2014-07-283-6/+10
| | | | | | | | | | | | | | | | | | This fixes 3D texture support in all these cases, because array_size is 1 with 3D textures and depth0 actually contains the "array size". util_max_layer is universal and returns the last layer index for any texture target. A lot of the cases below can't actually be hit with 3D textures, but let's be consistent. This fixes a failure in: piglit layered-rendering/clear-color-all-types 3d single_level for r600g and radeonsi, which was caused by an incorrect CMASK size calculation. Cc: [email protected] Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix occlusion queries on HawaiiMarek Olšák2014-07-281-1/+7
| | | | | | | This was just a guess - and it worked! Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* winsys/radeon: fix vram_size overflow with HawaiiMarek Olšák2014-07-281-1/+3
| | | | | | | This fixes piglit spec/!OpenGL 3.1/minmax. Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: fix a hang with streamout on HawaiiMarek Olšák2014-07-282-1/+14
| | | | | | | | | | | I actually couldn't reproduce this one, but internal docs recommend this workaround. Better safe than sorry. Also, the number of dwords for the sync packets is increased by 4 instead of 2, because it wasn't bumped last time when a new packet was added there. Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: fix a hang with instancing on HawaiiMarek Olšák2014-07-281-1/+15
| | | | | | | This fixes "piglit/bin/arb_transform_feedback2-draw-auto instanced". Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: fix CMASK and HTILE calculations for HawaiiMarek Olšák2014-07-281-2/+2
| | | | | | | | | | This fixes the checkerboard pattern in glxgears and anything that triggers fast color clear. num_channels is always <= 8, but Hawaii has 16 pipes. Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* r600g,radeonsi: add debug flags which disable tilingMarek Olšák2014-07-283-13/+24
| | | | Reviewed-by: Alex Deucher <[email protected]>
* gallium: rename shader cap MAX_CONSTS to MAX_CONST_BUFFER_SIZEMarek Olšák2014-07-2811-26/+26
| | | | | | | | | | This new name isn't so confusing. I also changed the gallivm limit, because it looked wrong. Reviewed-by: Brian Paul <[email protected]> v2: use sizeof(float[4])
* r600g: switch SNORM conversion to DX and GLES behaviorMarek Olšák2014-07-284-7/+0
| | | | | | | | | it also matches GL 4.2 further discussion: http://lists.freedesktop.org/archives/mesa-dev/2013-August/042680.html Cc: [email protected]
* ilo: correctly propagate resource renames to hardwareChia-I Wu2014-07-283-14/+30
| | | | | Not only should we mark states dirty when the underlying resource is renamed, we should also update the CSO bo when available.
* ilo: add ilo_resource_get_bo() helperChia-I Wu2014-07-282-17/+18
| | | | We will need it in the following commit.
* radeonsi: Use util_memcpy_cpu_to_le32()Tom Stellard2014-07-282-19/+8
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g/compute: Add debug information to promote and demote functionsBruno Jiménez2014-07-281-4/+11
| | | | | | | v2: Add information about the item's starting point and size v3: Rebased on top of master Reviewed-by: Tom Stellard <[email protected]>
* r600g/compute: Add documentation to compute_memory_poolBruno Jiménez2014-07-282-31/+86
| | | | | | v2: Rebased on top of master Reviewed-by: Tom Stellard <[email protected]>
* ilo: unblock an inline write with a staging boChia-I Wu2014-07-281-13/+31
| | | | This should allow a deeper pipeline.
* ilo: try unblocking a transfer with a staging boChia-I Wu2014-07-284-19/+209
| | | | | | | When mapping a busy resource with PIPE_TRANSFER_DISCARD_RANGE or PIPE_TRANSFER_FLUSH_EXPLICIT, we can avoid blocking by allocating and mapping a staging bo, and emit pipelined copies at proper places. Since the staging bo is never bound to GPU, we give it packed layout to save space.
* ilo: enable persistent and coherent transfersChia-I Wu2014-07-283-8/+35
| | | | Enable PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT and reorder caps a bit.
* ilo: drop ptr from ilo_transferChia-I Wu2014-07-282-35/+36
| | | | | With the recent clean-ups, we can pass the mapped pointer around between functions cleanly. Drop it to make ilo_transfer smaller.
* ilo: s/TRANSFER_MAP_UNSYNC/TRANSFER_MAP_GTT_UNSYNC/Chia-I Wu2014-07-282-6/+6
| | | | | It maps to drm_intel_gem_bo_map_unsynchronized(), which results in unsynchronized GTT mapping.
* ilo: drop unused context param from transfer functionsChia-I Wu2014-07-281-115/+100
| | | | Many of the transfer functions do not need an ilo_context. Drop it.
* ilo: tidy up transfer mapping/unmappingChia-I Wu2014-07-281-88/+89
| | | | | | Add xfer_map() to replace map_bo_for_transfer(). Add xfer_unmap() and xfer_alloc_staging_sys() to simplify texture and buffer mapping/unmapping, and enable more code sharing between them.
* ilo: tidy up choose_transfer_method()Chia-I Wu2014-07-281-84/+164
| | | | | | Add a bunch of helper functions and a big comment for choose_transfer_method(). This also fixes handling of PIPE_TRANSFER_MAP_DIRECTLY to not ignore tiling.
* ilo: free transfers with util_slab_free()Chia-I Wu2014-07-281-1/+1
| | | | We used FREE() in one of the error path.
* ilo: simplify ilo_flush()Chia-I Wu2014-07-263-20/+30
| | | | Move fence creation to the new ilo_fence_create().
* r600g/compute: Defrag the pool at the same time as we grow itBruno Jiménez2014-07-252-23/+19
| | | | | | | | | | | | This allows us two things: we now need less item copies when we have to defrag+grow the pool (to just one copy per item) and, even in the case where we don't need to defrag the pool, we reduce the data copied to just the useful data that the items use. Note: The fallback path is a bit ugly now, but hopefully we won't need it much. Reviewed-by: Tom Stellard <[email protected]>
* r600g/compute: Try to use a temporary resource when growing the poolBruno Jiménez2014-07-251-18/+43
| | | | | | | | | | | | | Now, before moving everything to host memory, we try to create a new resource to use as a pool. I we succeed we just use this resource and delete the previous one. If we fail we fallback to using the shadow. This should make growing the pool faster, and we can also save 64KB of memory that were allocated for the 'shadow', even if they weren't used. Reviewed-by: Tom Stellard <[email protected]>
* freedreno: fix typo in gpu version checkRob Clark2014-07-251-1/+1
| | | | | | | Opps, I should use larger fonts, I guess. Reported-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split out shader compiler from a3xxRob Clark2014-07-2525-477/+580
| | | | | | | | | | | | | | | | | | | | | | Move the bits we want to share between generations from fd3_program to ir3_shader. So overall structure is: fdN_shader_stateobj -> ir3_shader -> ir3_shader_variant -> ir3 |- ... \- ir3_shader_variant -> ir3 So the ir3_shader becomes the topmost generation neutral object, which manages the set of variants each of which generates, compiles, and assembles it's own ir. There is a bit of additional renaming to s/fd3_compiler/ir3_compiler/, etc. Keep the split between the gallium level stateobj and the shader helper object because it might be a good idea to pre-compute some generation specific register values (ie. anything that is independent of linking). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: rename ir3_shader to ir3Rob Clark2014-07-2512-55/+55
| | | | | | | | First step of reoganization split out compiler (so it can be shared between a3xx and a4xx). Rename ir3_shader -> ir3 (since we'll want the name ir3_shader for a higher level object). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: scheduler vs pred regRob Clark2014-07-252-3/+51
| | | | | | | The scheduler also needs to be aware of predicate register (p0) in addition to address register (a0). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: little cleanupsRob Clark2014-07-254-39/+19
| | | | | | Remove some obsolete comments, rename deref->addr. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: enable/disable wa's based on patch-levelRob Clark2014-07-254-8/+34
| | | | | | | | It seems like for the most part, different behaviors, workarounds, etc, should be conditional on GPU patch revision (ie. a320.0 vs a320.2) rather than GPU id (a320 vs a330). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: make IR heap dyanmicRob Clark2014-07-252-8/+43
| | | | | | | | | | | | The fixed size heap is a remnant of the fdre-a3xx assembler. Yet it is convenient for being able to free the entire data structure in one shot without worrying about leaking nodes. Change it to dynamically grow the heap size (adding chunks) as needed so we don't have an artificial upper limit on shader size (other than hw limits) and don't always have to allocate worst-case size. Signed-off-by: Rob Clark <[email protected]>
* r600g/compute: Fix singed/unsigned comparison compiler warnings.Jan Vesely2014-07-251-7/+7
| | | | | | | The iteration variables go from 0 anyway. Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* gallium: Add PIPE_CAP_COMPUTE_IMAGES_SUPPORTEDTom Stellard2014-07-251-0/+7
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
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