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* radeon/vce: use nblk_y instead of npix_yMarek Olšák2016-10-264-7/+7
* gallium/radeon: define RADEON_SURF_MODE_* as enumsMarek Olšák2016-10-262-9/+14
* gallium/radeon: stop using some input fields from radeon_surfaceMarek Olšák2016-10-264-20/+20
* gallium/radeon: fold r600_setup_surface into r600_init_surfaceMarek Olšák2016-10-261-38/+24
* gallium/radeon: fold radeon_winsys::surface_best into radeon/winsysMarek Olšák2016-10-262-13/+3
* gallium/radeon: use r600_gfx_write_event_eop everywhereMarek Olšák2016-10-263-23/+10
* gallium/radeon: make r600_gfx_write_fence more genericMarek Olšák2016-10-264-14/+34
* gallium/radeon: fix a ZPASS comment, EVENT_WRITE_EOP fixupsMarek Olšák2016-10-262-4/+4
* radeonsi: enable SDMA on Carrizo and all CIK chips againMarek Olšák2016-10-261-10/+0
* gallium/radeon: make sure the address of separate CMASK is aligned properlyMarek Olšák2016-10-261-2/+3
* gallium/radeon: fix incorrect bpe use in si_set_optimal_micro_tile_modeMarek Olšák2016-10-261-7/+7
* nir/i965/anv/radv/gallium: make shader info a pointerTimothy Arceri2016-10-263-5/+5
* nv50/ir: start LocalCSE with getFirst to merge PHI instructionsKarol Herbst2016-10-251-1/+1
* nvc0: use correct bufctx when invalidating CP texturesSamuel Pitoiset2016-10-251-1/+1
* nv50/ir: do not perform global membar for shared memorySamuel Pitoiset2016-10-241-1/+4
* nv50/ir: display OP_BAR subops in debug modeSamuel Pitoiset2016-10-241-0/+9
* nv50/ir: it appears that OP_DISCARD can't take a join modifierIlia Mirkin2016-10-221-0/+1
* nv50/ir: use levelZero for non-frag tex/txp opsIlia Mirkin2016-10-221-0/+5
* gallium: add PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERSIlia Mirkin2016-10-2215-0/+15
* nvc0/ir: remove outdated comment about SHLADDSamuel Pitoiset2016-10-222-2/+0
* vc4: Avoid making temporaries for assignments to NIR registers.Eric Anholt2016-10-211-35/+79
* vc4: Add a comment with discussion of how simulation works.Eric Anholt2016-10-211-0/+25
* vc4: Move simulator winsys mapping and tracking to the simulator.Eric Anholt2016-10-213-20/+56
* vc4: Move simulator memory management to a u_mm.h heap.Eric Anholt2016-10-215-41/+208
* vc4: Move simulator globals into a struct.Eric Anholt2016-10-212-34/+29
* vc4: Restructure the simulator mode.Eric Anholt2016-10-215-84/+182
* vc4: Fix termination of the initial scan for branch targets.Eric Anholt2016-10-211-11/+8
* radeonsi: fix a regression in si_eliminate_const_outputNicolai Hähnle2016-10-211-4/+3
* nv50,nvc0: don't keep track of whether fb rt0 is integer-onlyIlia Mirkin2016-10-216-44/+22
* nvc0: do not break 3D state by pushing MS coordinates on FermiSamuel Pitoiset2016-10-201-43/+44
* nvc0: translate compute shaders at program creationSamuel Pitoiset2016-10-201-0/+4
* radeonsi: fix build of si_eliminate_const_vs_outputs on LLVM <= 3.8Marek Olšák2016-10-201-3/+2
* radeonsi: fix 64-bit loads from LDSNicolai Hähnle2016-10-201-1/+1
* nv50/ir: process texture offset sources as regular sourcesIlia Mirkin2016-10-191-53/+94
* nv50,nvc0: avoid reading out of bounds when getting bogus so infoIlia Mirkin2016-10-192-2/+8
* nvc0/ir: simplify predicate logic for GK104 atomic operationsSamuel Pitoiset2016-10-191-14/+7
* nvc0/ir: remove useless NVC0LoweringPass::gMemBaseSamuel Pitoiset2016-10-191-4/+1
* nv50/ir: print CCTL subops in debug modeSamuel Pitoiset2016-10-191-0/+9
* radeonsi: eliminate trivial constant VS outputsMarek Olšák2016-10-193-2/+186
* nv50/ir: silent TGSI_PROPERTY_FS_DEPTH_LAYOUTSamuel Pitoiset2016-10-191-0/+1
* radeonsi: remove cb0_is_integer handlingMarek Olšák2016-10-193-13/+3
* svga: minor code improvements in svga_validate_pipe_sampler_view()Brian Paul2016-10-181-8/+8
* radeonsi: rename prefixes from radeon to siMarek Olšák2016-10-184-157/+157
* radeonsi: merge radeon_llvm_context and si_shader_contextMarek Olšák2016-10-184-317/+290
* radeonsi: import all TGSI->LLVM code from gallium/radeonMarek Olšák2016-10-1811-462/+346
* gallium/radeon: simplify initialization of 64-bit gallivm buildersMarek Olšák2016-10-181-18/+4
* gallium/radeon: remove unused radeon_llvm_reg_index_soaMarek Olšák2016-10-182-7/+0
* radeonsi: move LLVM ALU codegen into radeonsiMarek Olšák2016-10-186-992/+1056
* gm107/ir: fix bit offset of tex lod setting for indirect texturingIlia Mirkin2016-10-181-1/+1
* gm107/ir: fix texturing with indirect samplersIlia Mirkin2016-10-181-0/+10
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