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* radeonsi: move DB_RENDER_CONTROL into draw_vboMarek Olšák2014-09-015-58/+46
| | | | | | So that I can add fast depth clear. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: disable occlusion queries if they are not neededMarek Olšák2014-09-011-0/+8
| | | | | | | We always left them enabled, which turned off HiZ in some cases. This should improve performace with Hyper-Z. Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: force fast stencil and HTILE stencil off, fixing a Hyper-Z hangMarek Olšák2014-09-012-9/+14
| | | | | | | | | | | | | This should be as fast as no HTILE for stencil. I think we can still get full performance with depth-only rendering even if stencil is present in the buffer but not used, but I'm not 100% sure. This may be revisited when HiS and fast stencil clear are implemented. This fixes a hang in Brutal Legend. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64471 Reviewed-by: Michel Dänzer <[email protected]>
* r600g: set VGT_ENHANCE=4 on R7xxMarek Olšák2014-09-012-0/+2
| | | | | | | This is a golden setting on RV740, but there is a hw bug which recommends setting it on all R7xx chipsets. Acked-by: Michel Dänzer <[email protected]>
* r600g: expose AMD_vertex_shader_layer and *_viewport_index on R600-R700Marek Olšák2014-09-011-1/+1
| | | | | | already implemented Acked-by: Michel Dänzer <[email protected]>
* r600g: fix layered clearMarek Olšák2014-09-011-1/+2
| | | | | Cc: [email protected] Acked-by: Michel Dänzer <[email protected]>
* r600g: some DB bug workarounds for R6xx DB flushingMarek Olšák2014-09-011-0/+7
| | | | Acked-by: Michel Dänzer <[email protected]>
* r600g: enable fast depth clear for array textures and cubemapsMarek Olšák2014-09-011-1/+2
| | | | | | I have a piglit test that hits this. Acked-by: Michel Dänzer <[email protected]>
* r600g: use HTILE allocator from SIMarek Olšák2014-09-013-47/+23
| | | | | | | | | | | | It's almost the same. This enables tiling for HTILE. It also enables Hyper-Z for other texture targets (1D, 1D_ARRAY, 2D_ARRAY, CUBE, CUBE_ARRAY, 3D, RECT). 2D array depth textures are tested by Unigine Sanctuary and my new piglit test. Acked-by: Michel Dänzer <[email protected]>
* r600g: set DB_DEPTH_SIZE.HEIGHT_TILE_MAX for EG/CM, inline other fieldsMarek Olšák2014-09-011-9/+12
| | | | | | | | This fixes rendering to non-zero layer/face/slice with HTILE. v2: added the assertion Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: set DB_DEPTH_SIZE.HEIGHT_TILE_MAX, inline other fieldsMarek Olšák2014-09-011-9/+8
| | | | | | | | | | This fixes rendering to a non-zero layer/face/slice with HTILE. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72685 v2: added the assertion Reviewed-by: Michel Dänzer <[email protected]>
* r600g: Implement sm5 geometry shader instancingGlenn Kennard2014-09-013-2/+14
| | | | | | Requires Evergreen or later hardware. Signed-off-by: Glenn Kennard <[email protected]>
* ilo: set INTEL_RELOC_GGTT only on GEN6Chia-I Wu2014-08-311-7/+17
| | | | We asked MI commands to use GGTT only on GEN6.
* ilo: fix bound check for 3DSTATE_URB_VSChia-I Wu2014-08-311-3/+3
| | | | Fix max/min entries on GEN7.5 GT2/GT3.
* ilo: replace cmd by dw0 in GPEChia-I Wu2014-08-312-167/+236
| | | | | With e3c251071b0c9396c3ec76d1cf943c60ae297281, the magic values are gone. We no longer need "cmd" to hide them. Replace it by dw0.
* freedreno/ir3: fix potential null ptr derefRob Clark2014-08-301-1/+2
| | | | | | Fix potential segfault in debug code. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add TXBRob Clark2014-08-301-0/+5
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: detect scheduler failRob Clark2014-08-303-4/+21
| | | | | | | | | | | | | | | | | | | | There are some cases where the scheduler can get itself into impossible situations, by scheduling the wrong write to pred or addr register first. (Ie. it could end up being unable to schedule any instruction if some instruction which depends on the current addr/reg value also depends on another addr/reg value.) To solve this we'd need to be able to insert extra mov instructions (which would also help when register assignment gets into impossible situations). To do that, we'd need to move the nop padding from sched into legalize. But to start with, just detect when we get into an impossible situation and bail, rather than sitting forever in an infinite loop. This way it will at least fall back to the old compiler, which might even work if you are lucky. Signed-off-by: Rob Clark <[email protected]>
* softpipe: handle vertex texture sampling when using llvm for drawRoland Scheidegger2014-08-309-36/+209
| | | | | | | | | | | | | Pretty trivial, just fill in the offsets and such. The implementation is near 100% copy and paste from llvmpipe. Should be useful for debugging. No piglit change when not using SOFTPIPE_USE_LLVM=1. Now that it can do the same tests with and without using llvm for vs/gs, with llvm more pass, the only things failing only with llvm seems to be edgeflags tests and vs/gs-pow-float-float (and for the latter I'm not convinced the zero tolerance it requires is somehow mandated by glsl). Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: (trivial) enable cube map arraysRoland Scheidegger2014-08-301-1/+2
| | | | | | | | The code is all in place now so enable it. Seems to pass all relevant piglit tests (just like cube maps, some of the cube map array tests need GALLIVM_DEBUG=no_quad_lod,no_rho_approx) Reviewed-by: Jose Fonseca <[email protected]>
* softpipe: don't assert on illegal wrap mode for rect texturesRoland Scheidegger2014-08-301-2/+2
| | | | | | | | | | | | | | piglit tex-miplevel-selection nowadays doesn't use repeat wrap mode due to sampler objects any longer, however at the time of the clear the wrap mode is still illegal and at this point we get to verify the state, including samplers (even though they won't get used), and because mesa doesn't treat it as an incomplete texture as the spec says it should, we hit the assertion. Just warn about this for now instead. Gets crashes down from 44 to 14 in a piglit run (all were in various tests of tex-miplevel-selection with texture rectangles). Though just about all tex-miplevel-selection tests fail anyway for other reasons. Reviewed-by: Jose Fonseca <[email protected]>
* r600/compute: Don't leak compute pool item_list/unallocated_listAaron Watry2014-08-291-0/+6
| | | | | | | | v3: Fix multi-line comment format v2: Change to C-style comments and fix indentation Signed-off-by: Aaron Watry <[email protected]> Reviewed-by: Bruno Jiménez <[email protected]>
* r600g: Reinstate include path to common radeon source directoryMichel Dänzer2014-08-291-1/+2
| | | | | | | | | | | | Fixes build failure since commit a131263a2f19507ca0d2f6093672d930a7c054d1 ('gallium/radeon: cleanup header inclusion'): ../../../../../src/gallium/drivers/r600/evergreen_compute.c:50:30: fatal error: radeon_llvm_util.h: No such file or directory #include "radeon_llvm_util.h" ^ compilation terminated. Trivial.
* nouveau: allow more tokens by default to avoid parse failuresIlia Mirkin2014-08-281-2/+4
| | | | | | Also print a note saying that parsing failed to help isolate issues. Signed-off-by: Ilia Mirkin <[email protected]>
* gallium/radeon: cleanup header inclusionEmil Velikov2014-08-2831-36/+34
| | | | | | | | | | | | | | - Add top_srcdir/src/gallium/winsys to GALLIUM_DRIVER_C{XXFLAGS}. - Remove top_srcdir/src/gallium/drivers/radeon from the includes. As a result: - Common radeon headers are prefixed with 'radeon/' - Winsys header inclusion is prefixed 'radeon/drm' Cc: Marek Olšák <[email protected]> Cc: Michel Dänzer <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/ilo: cleanup intel_winsys.hEmil Velikov2014-08-283-3/+312
| | | | | | | | | | | | | | | | Make the header location, inclusion and contents more common with its i915,r* and nouveau counterparts: - Move the header within drivers/ilo. - Separate out intel_winsys_create_for_fd into 'drm_public' header. - Cleanup the compiler includes. v2: Move the header to drivers/ilo. Suggested by Chia-I. v3: Correct intel_winsys.h inclusion. Spotted by Chia-I. Cc: Chia-I Wu <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* gallium: add cap for MAX_VERTEX_ATTRIB_STRIDETimothy Arceri2014-08-2713-0/+32
| | | | | Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* draw: fix base instance handling in llvm pathRoland Scheidegger2014-08-282-2/+2
| | | | | | | | | | | | | The base instance needs to be passed to the jited function, otherwise the instanced data fetch will only work with the same start instance when the jit function was created (and baking that into the key instead is not a viable option). This fixes piglit arb_base_instance-drawarrays (modulo some unrelated core/compat context trouble I get for the test). And fix the pipe cap bit in llvmpipe for it now that it actually works (it already worked for softpipe). Reviewed-by: Jose Fonseca <[email protected]>
* radeon/uvd: remove comment about RV770Alex Deucher2014-08-271-1/+0
| | | | | | | It doesn't seem to support field based decode after testing. Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: fix field handling on R6XX style UVDChristian König2014-08-261-2/+5
| | | | | | The first UVD generation can only do frame based output. Signed-off-by: Christian König <[email protected]>
* ilo: use genhw command opcodesChia-I Wu2014-08-265-134/+184
| | | | | Replace ILO_GPE_MI and ILO_GPE_CMD with magic values by descriptive genhw macros.
* ilo: rename intel_bo_map_unsynchronized()Chia-I Wu2014-08-262-9/+8
| | | | Rename it to intel_bo_map_gtt_async().
* ilo: remove max_batch_sizeChia-I Wu2014-08-263-8/+1
| | | | | It is used to derive an artificial limit on max relocs per bo. We choose not to export it anymore.
* ilo: replace domains by reloc flagsChia-I Wu2014-08-269-93/+47
| | | | | It is simpler and is supported by the kernel. It cannot be used with libdrm_intel yet though.
* radeonsi: handle PIPE_BIND_BLENDABLEMarek Olšák2014-08-251-1/+5
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r600g: only set PIPE_BIND_BLENDABLE if colorbuffer rendering is supportedMarek Olšák2014-08-252-20/+10
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r300g: handle PIPE_BIND_BLENDABLEMarek Olšák2014-08-251-1/+44
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* vc4: Stop doing qpu_inst(add, NOP) or qpu_inst(NOP, mul).Eric Anholt2014-08-241-84/+47
| | | | | Now that the extra WADDR is set, we can knock this off. Saves a lot of typing, and makes this code much more legible.
* vc4: Set the other WADDR in the qpu instruction helpers.Eric Anholt2014-08-241-1/+5
| | | | | Now you don't need to qpu_inst() your instruction with a NOP to get the other waddr set.
* vc4: Merge qpu_a_NOP() and qpu_m_NOP to a single qpu_NOP() helper.Eric Anholt2014-08-243-57/+45
| | | | | | Now that qpu_inst() ignores the WADDR from the other half of the instruction, we can set both the ADD and MUL WADDRs in the NOP helper. Thanks to that, we also no longer need to qpu_inst(NOP, NOP).
* vc4: Ignore WADDRs from the other half of the instruction when merging.Eric Anholt2014-08-241-1/+2
| | | | | | This allows setting the opposite-side WADDR to NOP (a non-zero value) in qpu_* helpers, so that we don't need to qpu_inst() merge them with NOPs all the time just to get the waddr set.
* vc4: Fix LT/GE set-0-or-1 compares.Eric Anholt2014-08-241-1/+1
| | | | | We were using the integer sub, which worked for the common case of EQ and NE. Fixes fs-lessThan-ivec2-ivec2 and other tests.
* freedreno/a2xx: fix segfaultRob Clark2014-08-241-0/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: handle first/last level properlyRob Clark2014-08-243-9/+13
| | | | | | Fixes some assumptions about first_level being zero. Signed-off-by: Rob Clark <[email protected]>
* freedreno: implement pipe_flush_resource()Rob Clark2014-08-241-1/+5
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: don't ignore src/dst levelRob Clark2014-08-241-39/+63
| | | | | | Don't ignore src/dst_level in pipe_copy_region. Signed-off-by: Rob Clark <[email protected]>
* vc4: Fix save/restore of the VS/FS in the blitter.Eric Anholt2014-08-231-2/+2
| | | | | | When I made the shader cache take the .fs member and moved the binding point to .bind_fs, I failed to update these. Fixes crashes in copyteximage-related tests.
* vc4: Clear padding of ioctl arguments.Eric Anholt2014-08-231-0/+1
| | | | Fixes valgrind complaints from valgrind being unaware of our ioctls.
* vc4: Add support for fragment discards.Eric Anholt2014-08-224-0/+43
| | | | | | Fixes piglit glsl-fs-discard-01 and -03, and allows a lot of mesa demos to start running. glsl-fs-discard-02 has a problem where the first tile is not getting stored on the first render.
* vc4: Make some helpers for setting condition codes in instructions.Eric Anholt2014-08-223-15/+27
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