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* ilo: new pipe driver for Intel GEN6+Chia-I Wu2013-04-2628-0/+4887
| | | | | This commit adds some boilerplate code. The header files found under include/ are copied from i965.
* winsys/radeon: consolidate tracing into winsys v2Jerome Glisse2013-04-2511-66/+22
| | | | | | | | | | | | This move the tracing timeout and printing into winsys and add an debug environement variable for it (R600_DEBUG=trace_cs). Lot of file touched because of winsys API changes. v2: Do not write lockup file if ib uniq id does not match last one Signed-off-by: Jerome Glisse <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g/compute: Removed unused and untested codeTom Stellard2013-04-255-776/+66
| | | | | | | | There was a lot of code in evergreen_compute_internal.c that was not being used at all and most of it was duplicating code from other parts of the driver. Reviewed-by: Alex Deucher <[email protected]>
* r600g/compute: Use a constant buffer to store kernel parameters v2Tom Stellard2013-04-252-16/+30
| | | | | | | | | v2: - Fix usage of set_constant_buffer() - Fix typo in comment Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: Add evergreen_emit_cs_constant_buffers() v2Tom Stellard2013-04-253-11/+36
| | | | | | | | v2: - Bump R600_NUM_ATOMS Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g/compute: Don't use radeon_winsys::buffer_wait() after dispatching a kernelTom Stellard2013-04-251-6/+0
| | | | | | | The state tracker should be responsible for waiting for the kernel to finish. Reviewed-by: Alex Deucher <[email protected]>
* r600g/compute: Fix input buffer size calculationTom Stellard2013-04-251-1/+1
| | | | | | Buffer size should be in bytes not dwords. Reviewed-by: Alex Deucher <[email protected]>
* freedreno: use writecombine buffersRob Clark2013-04-251-1/+2
| | | | | | | Better than uncached for writes, which are common for vertex buffer upload, etc. Signed-off-by: Rob Clark <[email protected]>
* freedreno: don't patch and re-emit same shader as muchRob Clark2013-04-255-64/+65
| | | | | | | | New textures or vertex buffers don't always require patching and re-emitting the shaders. So do a better job of figuring out when we actually have to patch the shader. Signed-off-by: Rob Clark <[email protected]>
* trace: Only close trace files on exit.José Fonseca2013-04-253-18/+4
| | | | | | Many applications don't exit cleanly, others may create and destroy a screen multiple times, so we only write </trace> tag and close at exit time.
* scons: Support clang.José Fonseca2013-04-251-1/+1
| | | | | | | | | | | clang is supports most gcc options / extensions, with a some exceptions. The biggest advantage of using clang is that compilation times are much short. One can tell scons to use clang when building by invoking it as CC=clang CXX=clang++ scons libgl-xlib
* scons: Remove redundant code.José Fonseca2013-04-251-3/+0
| | | | -fvisibility=hidden is already elsewhere for the whole tree.
* freedreno: fix bogus IMM const reg indexRob Clark2013-04-242-3/+3
| | | | | | | | We were assigning incorrect const register for immediates, and potentially writing immediate const to the wrong location. This fixes an incorrect-rendering bug with xonotic. Signed-off-by: Rob Clark <[email protected]>
* freedreno: clear fixes and debuggingRob Clark2013-04-244-1/+29
| | | | | | | | Set a few extra registers to make sure we are in proper state for clearing. And also add some debug options to mark all state dirty in clear and gmem operations to aid in debugging. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix texture fetch typeRob Clark2013-04-244-2/+10
| | | | | | | There is a bit we need to set for 2D vs 3D fetch, to tell the hw whether there are two or there valid input components. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix temp register usageRob Clark2013-04-241-48/+52
| | | | | | | | | | | | | | | The previous approach of using the dst register as an intermediate temporary doesn't work in a lot of cases. For example, if the dst register is the same as one of the src registers. For now, just simplify it and always allocate a new register to use as an intermediate. In some cases this will result in more registers used than required. I think the best solution would be to implement an optimization pass to reduce the number of registers used, which would also solve the problem we have now of not being able to use GPRs that are assigned for TGSI_FILE_INPUT. Signed-off-by: Rob Clark <[email protected]>
* freedreno: use u_math macros/helpers moreRob Clark2013-04-246-25/+20
| | | | | | | | | Get rid of a few self-defined macros: ALIGN() -> align() min() -> MIN2() max() -> MAX2() Signed-off-by: Rob Clark <[email protected]>
* freedreno: implement fd_screen_destroy()Rob Clark2013-04-241-6/+26
| | | | | | | | Opps, didn't notice that I had left it stubbed out. Also, make things fail a bit more gracefully when things go wrong. Signed-off-by: Rob Clark <[email protected]>
* freedreno: set SWAP bit based on formatRob Clark2013-04-241-7/+19
| | | | | | | | Really this should be set based on buffer format, not on color vs depth/stencil. Probably there should be more formats that set the bit as we add support for more render target formats. Signed-off-by: Rob Clark <[email protected]>
* radeon/llvm: Fix segfault with a specifc libelf implementationTom Stellard2013-04-241-0/+4
| | | | | | | | The libelf implementation that is distributed here: http://www.mr511.de/software/english.html requires calling elf_version() prior to calling elf_memory() Tested-by: Michel Dänzer <[email protected]>
* r600g: use CP DMA for buffer clears on evergreen+Alex Deucher2013-04-244-2/+119
| | | | | | | | | | Lighter weight then using streamout. Only evergreen and newer asics support embedded data as src with CP DMA. Reviewed-by: Jerome Glisse <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* r600g/llvm: Pass struct r600_bytecode to r600_llvm_compileTom Stellard2013-04-243-8/+7
| | | | | | This way we don't need to update the function signature everytime we emit a new config value. This also fixes the build with --enable-opencl.
* radeonsi: cleanup disabling tiling for UVD v3Christian König2013-04-241-3/+4
| | | | | | | | | | Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=63702 v2: add a comment that this is just a workaround v3: fix typo in comment Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* mesa: Restore 78-column wrapping of license text in C-style comments.Kenneth Graunke2013-04-2380-320/+320
| | | | | | | | | | | | | | The previous commit introduced extra words, breaking the formatting. This text transformation was done automatically via the following shell command: $ git grep 'THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY' | sed 's/:.*$//' | xargs -I {} sh -c 'vim -e -s {} < vimscript where 'vimscript' is a file containing: /THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY/;/\*\// !fmt -w 78 -p ' * ' :wq Reviewed-by: Brian Paul <[email protected]>
* mesa: Add "OR COPYRIGHT HOLDERS" to license text disclaiming liability.Kenneth Graunke2013-04-2380-80/+80
| | | | | | | | | | | | | | | This brings the license text in line with the MIT License as published on the Open Source Initiative website: http://opensource.org/licenses/mit-license.php Generated automatically be the following shell command: $ git grep 'THE AUTHORS BE LIABLE' | sed 's/:.*$//g' | xargs -I '{}' \ sed -i 's/THE AUTHORS/THE AUTHORS OR COPYRIGHT HOLDERS/' {} This introduces some wrapping issues, to be fixed in the next commit. Reviewed-by: Brian Paul <[email protected]>
* gallium: Replace gl_rasterization_rules with lower_left_origin and ↵José Fonseca2013-04-2317-49/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | half_pixel_center. Squashed commit of the following: commit 04c5fa2cbb8e89d6f2fa5a75af1cca03b1f6b852 Author: José Fonseca <[email protected]> Date: Tue Apr 23 17:37:18 2013 +0100 gallium: s/lower_left_origin/bottom_edge_rule/ commit 4dff4f64fa83b9737def136fffd161d55e4f1722 Author: José Fonseca <[email protected]> Date: Tue Apr 23 17:35:04 2013 +0100 gallium: Move diagram to docs. commit 442a63012c8c3c3797f45e03f2ca20ad5f399832 Author: James Benton <[email protected]> Date: Fri May 11 17:50:55 2012 +0100 gallium: Replace gl_rasterization_rules with lower_left_origin and half_pixel_center. This change is necessary to achieve correct results when using OpenGL FBOs. Reviewed-by: Marek Olšák <[email protected]>
* r600g: initialize CMASK and HTILE with the GPU using streamoutMarek Olšák2013-04-234-7/+80
| | | | | | | | | | | | | This fixes a crash when a resource cannot be mapped to the CPU's address space because it's too big. This puts a global pipe_context in r600_screen, which is guarded by a mutex, so that we can use pipe_context when there isn't one around. Hopefully our multi-context support is solid. Reviewed-by: Alex Deucher <[email protected]> NOTE: This is a candidate for the 9.1 branch.
* r600/llvm: Read stacksize from config headerVincent Lejeune2013-04-234-3/+5
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* /bin/bash: q : commande introuvableVincent Lejeune2013-04-232-2/+2
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* radeon/llvm: Fix build with LLVM >= r180063Tom Stellard2013-04-231-0/+1
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* softpipe: fix streamout with an emptry geometry shaderZack Rusin2013-04-222-12/+23
| | | | | | | | | Same approach as in the llvmpipe, if the geometry shader is null and we have stream output then attach it to the vertex shader right before executing the draw pipeline. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* llvmpipe: verify function on blend test.José Fonseca2013-04-211-0/+2
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* llvmpipe: Don't support Z32_FLOAT_S8X24_UINT texture sampling support either.José Fonseca2013-04-201-4/+6
| | | | | | | Because we don't support, and the u_format fallback doesn't work for zs formats. Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: Ignore depth-stencil state if format has no depth/stencil.José Fonseca2013-04-201-4/+10
| | | | | | Prevents assertion failures inside the driver for such state combinations. Reviewed-by: Brian Paul <[email protected]>
* freedreno: move ir -> ir2Rob Clark2013-04-206-283/+283
| | | | | | | | There will be a new IR for a3xx, which has a very different shader ISA (more scalar oriented). So rename to avoid conflicts later when I start adding a3xx support to the gallium driver. Signed-off-by: Rob Clark <Rob Clark [email protected]>
* freedreno: cleanup some cruft left over from fdreRob Clark2013-04-202-133/+1
| | | | | | | | The standalone shader assembler needed some meta-data to know about attributes/varyings/etc, to do the shader linkage. We don't need these parts with gallium/tgsi, so just get rid of it. Signed-off-by: Rob Clark <Rob Clark [email protected]>
* svga: remove TGSI_OPCODE_BREAKC instruction translationRoland Scheidegger2013-04-201-1/+0
| | | | | | | While initially that opcode probably was meant for something along the lines of sm3 break_comp it has never worked that way (not even the argument count was right) and now the opcode has quite different semantics so just remove it. (Discovered by Jose Fonseca)
* svga: whitespace, comment fixes in svga_pipe_query.cBrian Paul2013-04-191-41/+49
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* svga: whitespace, comment fixes in svga_pipe_fs/vs.cBrian Paul2013-04-192-48/+41
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* radeonsi: add support for compressed texture v2Jerome Glisse2013-04-182-2/+76
| | | | | | | | | | Most test pass, issue are with border color and swizzle. Based on ircnick<maelcum> patch. v2: Restaged commit hunk Signed-off-by: Jerome Glisse <[email protected]>
* radeonsi: add 2d tiling support for texture v3Jerome Glisse2013-04-182-72/+20
| | | | | | | | v2: Remove left over code v3: Restage properly the commit so hunk of first one are not in second one. Signed-off-by: Jerome Glisse <[email protected]>
* llvmpipe: Take in consideration all current constant buffers when mapping.José Fonseca2013-04-181-3/+9
| | | | | Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Zack Rusin <[email protected]>
* nv50: add remaining RGBX formatsChristoph Bumiller2013-04-181-4/+12
| | | | | | | | Not all are supported as render targets. The state tracker fallback of using RGBA instead of RGBX currently fails for blending, we could work around this by clearing their alpha to 1 and modifying the color mask to disable writing alpha.
* st/mesa: optionally apply texture swizzle to border color v2Christoph Bumiller2013-04-1811-0/+18
| | | | | | | | | | | | This is the only sane solution for nv50 and nvc0 (really, trust me), but since on other hardware the border colour is tightly coupled with texture state they'd have to undo the swizzle, so I've added a cap. The dependency of update_sampler on the texture updates was introduced to avoid doing the apply_depthmode to the swizzle twice. v2: Moved swizzling helper to u_format.c, extended the CAP to provide more accurate information.
* nv50: set BORDER_COLOR_SRGB in sampler objectsChristoph Bumiller2013-04-182-19/+35
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* nv50: fix 4th component of Lx_SINT/UINT formatsChristoph Bumiller2013-04-181-6/+6
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* r600g: Fix build with --enable-openclTom Stellard2013-04-181-1/+2
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* llvmpipe: Support half integer pixel center fs coord.José Fonseca2013-04-184-3/+28
| | | | | | | Tested with graw/fs-fragcoord 2/3, and piglit glsl-arb-fragment-coord-conventions. Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: Remove the static interpolation.José Fonseca2013-04-183-384/+19
| | | | | | | | No longer used. If we ever want the old behavior we can run a loop unroller pass. Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: Drop pos arg from lp_build_tgsi_soa.José Fonseca2013-04-181-2/+2
| | | | | | Never used. Reviewed-by: Roland Scheidegger <[email protected]>
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