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* r600g/sb: fix constant propagation in gvn passVadim Girlin2013-05-031-1/+2
| | | | | | Fixes the bug that prevented propagation of literals in some cases. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: don't run unnecessary passesVadim Girlin2013-05-031-3/+0
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: silence warnings with gcc 4.8Vadim Girlin2013-05-032-14/+15
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix handling of interference sets in post_schedulerVadim Girlin2013-05-032-8/+8
| | | | | | | | | | | post_scheduler clears interference set for reallocatable values when the value becomes live first time, and then updates it to take into account modified order of operations, but this was not handled properly if the value appears first time as a source in copy operation. Fixes issues with webgl demo: http://madebyevan.com/webgl-water/ Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix allocation of indirectly addressed input arraysVadim Girlin2013-05-034-10/+25
| | | | | | | | | Some inputs may be preloaded into predefined GPRs, so we can't reallocate arrays with such inputs. Fixes issues with webgl demo: http://oos.moxiecode.com/js_webgl/snake/ Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: use hex instead of binary constantsVadim Girlin2013-05-035-15/+15
| | | | | | This should fix build issues with GCC < 4.3 Signed-off-by: Vadim Girlin <[email protected]>
* r600g: use old shader disassembler by defaultVadim Girlin2013-05-034-19/+18
| | | | | | | | | | | | | | New disassembler is not completely isolated yet from further processing in r600g/sb that is not required for printing the dump, so it has higher probability to fail in case of any unexpected features in the bytecode. This patch adds "sbdisasm" flag for R600_DEBUG that allows to use new disassembler in r600g/sb for shader dumps when shader optimization is not enabled. If shader optimization is enabled, new disassembler is used by default. Signed-off-by: Vadim Girlin <[email protected]>
* radeon/uvd: enable interlaced buffers by defaultChristian König2013-05-032-5/+5
| | | | | | Kills tilling on UVD buffers, but we currently don't really need that. Signed-off-by: Christian König <[email protected]>
* vl/idct: fix for commit 7d2f2a0c890b1993532a45c8c392c28950ddc06eChristian König2013-05-032-6/+6
| | | | | | | | We still need the option for handling 3D textures as well. Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=64143 Signed-off-by: Christian König <[email protected]>
* vl/buffers: fix typo in function nameChristian König2013-05-032-6/+6
| | | | Signed-off-by: Christian König <[email protected]>
* radeon/uvd: fix some MPEG4 artifactsChristian König2013-05-031-7/+17
| | | | | | Still not perfect, but a step in the right direction. Signed-off-by: Christian König <[email protected]>
* ilo: use u_reduced_prims_for_vertices()Chia-I Wu2013-05-031-68/+1
| | | | We do not need our own prim_count() anymore.
* r600g: Don't set the dest cache bits on surface sync for ↵Tom Stellard2013-05-021-15/+13
| | | | | | | | | | | | | R600_CONTEXT_FLUSH_AND_INV We are already emitting a EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT packet when this flush flag is set, so flushing the dest caches with a SURFACE_SYNC should not be necessary. The motivation for this change is that emitting a SURFACE_SYNC packet with the CB bits set was causing compute shaders to hang on Cayman. Reviewed-by: Alex Deucher <[email protected]>
* r600g/compute: Fix build error in debug codeTom Stellard2013-05-021-1/+1
| | | | Reviewed-by: Alex Deucher <[email protected]>
* radeon: Fix build with LLVM 3.3Armin K2013-05-021-1/+1
| | | | Reviewed-by: Tom Stellard <[email protected]>
* r600/sb: Fix build failure with non-standard libdrm installation prefixLauri Kasanen2013-05-021-0/+1
| | | | | | Just like radeon/uvd, r600/sb fails to find the libdrm includes. Signed-off-by: Lauri Kasanen <[email protected]>
* radeon/uvd: Fix build failure with non-standard libdrm installation prefixLauri Kasanen2013-05-021-1/+1
| | | | | | | | | | Without this patch, radeon_uvd failed to find the libdrm includes: In file included from radeon_uvd.c:48: ../../winsys/radeon/drm/radeon_winsys.h:44:35: error: libdrm/radeon_surface.h: No such file or directory Signed-off-by: Lauri Kasanen <[email protected]>
* radeon/uvd: fix quant scan order for mpeg2Christian König2013-05-011-2/+6
| | | | Signed-off-by: Christian König <[email protected]>
* vl/buffer: use 2D_ARRAY instead of 3D texturesChristian König2013-05-012-14/+14
| | | | Signed-off-by: Christian König <[email protected]>
* ilo: fix PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERSChia-I Wu2013-05-011-0/+2
| | | | On GEN7+, is->dev.has_gen7_sol_reset is required.
* ilo: enable SO support on GEN7Chia-I Wu2013-05-011-3/+4
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* ilo: reset SO write offsets for new SO targetsChia-I Wu2013-05-011-6/+15
| | | | | When the SO targets are changed and no appending is requested, we need to send SOL_RESET on GEN7+.
* ilo: correctly program SO states for GEN7Chia-I Wu2013-05-011-7/+46
| | | | With the commands supported by GPE, we can finally program the states.
* ilo: implement GEN7 SO GPE functionsChia-I Wu2013-05-013-40/+150
| | | | They were just stubs before.
* ilo: add gen6_pipeline_update_max_svbi()Chia-I Wu2013-05-012-13/+35
| | | | | Move max_svbi calculation to a helper function and make it available for other GENs.
* ilo: expose register indices of OUTs in ilo_shaderChia-I Wu2013-05-014-4/+30
| | | | | pipe_stream_output_info tells us which of OUT[i] needs to be written out. We need the info to map OUT[i] to VUE offset.
* ilo: allow one-off flags to be specified for CPChia-I Wu2013-05-012-0/+15
| | | | It will be used for SOL_RESET on GEN7.
* ilo: fix tiling/size for special-purpose resourcesChia-I Wu2013-05-011-2/+30
| | | | We do not allocate such resources yet though.
* ilo: use UMS layout for render targetsChia-I Wu2013-05-014-19/+117
| | | | | As we do not advertise MSAA support, this change should not make any difference yet.
* ilo: support and prefer compact array spacingChia-I Wu2013-05-014-15/+77
| | | | | There is no reason to waste the memory when the HW can support compact array spacing (ARYSPC_LOD0).
* ilo: move device limits to ilo_dev_info or to GPEsChia-I Wu2013-05-0110-96/+127
| | | | It seems a bit weird to have device limits in a context.
* ilo: use ilo_dev_info in toy compilerChia-I Wu2013-05-0110-33/+33
| | | | | We need only dev->gen, but it makes sense to expose other information to the compiler.
* ilo: use ilo_dev_info in GPE and 3D pipelineChia-I Wu2013-05-0112-597/+587
| | | | | We need only dev->gen and dev->gt, but it makes sense to expose other information to the pipeline.
* ilo: add ilo_dev_info shared by the screen and contextsChia-I Wu2013-05-019-51/+71
| | | | | The struct is used to describe the device information, such as PCI ID, GEN, GT, and etc.
* ilo: fix indentation of ilo_gpe_gen*.hChia-I Wu2013-05-012-258/+258
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* r600g/sb: remove unused codeVadim Girlin2013-04-302-34/+0
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: collect shader statisticsVadim Girlin2013-04-305-8/+162
| | | | | | | | | Collects various statistical information for each shader and total stats for contexts. Printed with R600_DEBUG=sb,sbstat Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: don't propagate dead values in GVN passVadim Girlin2013-04-301-0/+3
| | | | | | | | | | | | | | In some cases we use value::gvn_source field to link values that are known to be equal before gvn pass (e.g. results of DOT4 in different slots of the same alu group), but then source value may become dead later and this confuses further passes. This patch resets value::gvn_source to NULL in the dce_cleanup pass if it points to dead value. Fixes segfault during shader optimization with ETQW. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: use simple heuristic to limit register pressureVadim Girlin2013-04-302-3/+33
| | | | | | | | | | | | | | | | | | | | | It's not a complete register pressure tracking, yet it helps to prevent register allocation problems in some cases where they were observed. The problems are uncovered by false dependencies between fetch instructions introduced by some recent changes in TGSI and/or default backend. Sometimes we have code like this: ... SAMPLE R5.xyzw, R5.xyzw ... store R5.xyzw somewhere MOV R5.x, <next x coord> MOV R5.y, <next y coord> SAMPLE R5.xyzw, R5.xyzw ... <may be repeated a lot of times> With 2D resources, z and w in SAMPLE src reg aren't used and can be simply masked, but shader backend doesn't have this information, so it's considered as data dependency by optimization algorithms.
* r600g/sb: improve error checking in ra_coalesce passVadim Girlin2013-04-302-14/+27
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* r600g/sb: use source bytecode in case of optimization errorsVadim Girlin2013-04-305-11/+25
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* r600g: plug in optimizing backendVadim Girlin2013-04-308-3/+155
| | | | | | Optimization is enabled with "R600_DEBUG=sb". Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: initial commit of the optimizing shader backendVadim Girlin2013-04-3035-0/+17498
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* r600g: use enum type for domains field in struct r600_resourceVadim Girlin2013-04-301-1/+1
| | | | This prevents the problems when the header is included in C++ code.
* r600g: add new flags to isa instruction tablesVadim Girlin2013-04-301-116/+127
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* r600g: always create reverse lookup isa tablesVadim Girlin2013-04-301-10/+2
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* r600g: mask unused source components for SAMPLEVadim Girlin2013-04-301-0/+20
| | | | | | | | This results in more clean shader code and may improve the quality of optimized code produced by r600-sb due to eliminated false dependencies in some cases. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/llvm: Fix opencl buildVincent Lejeune2013-04-301-1/+1
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* r600g/llvm: get use_kill from compiler shaderVincent Lejeune2013-04-304-2/+9
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* llvmpipe: Fix queries when screen->num_threads == 0.José Fonseca2013-04-291-2/+3
| | | | | | | | | | That is, when llvmpipe is run in single-threaded mode. Trivial. Tested with LP_NUM_THREADS=0 glean --run results --overwrite --quick --tests occluQry
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