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* gallium: add PIPE_CAP_TEXTURE_MULTISAMPLEMarek Olšák2012-09-3010-0/+10
| | | | | Tested-by: Michel Dänzer <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* softpipe: fix set_framebuffer_state with uninitialized surfaces past nr_cbufs-1Marek Olšák2012-09-301-3/+5
| | | | | Tested-by: Michel Dänzer <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* r600g: add some members to radeon_llvm_contextVincent Lejeune2012-09-282-0/+11
| | | | Reviewed-by: Tom Stellard <[email protected]>
* r600g: tgsi-to-llvm path is taken after declarations have been parsedVincent Lejeune2012-09-281-26/+32
| | | | Reviewed-by: Tom Stellard <[email protected]>
* r600g: fix EXP on CaymanMarek Olšák2012-09-271-4/+2
| | | | NOTE: This is a candidate for the stable branches.
* r600g: fix RSQ of negative value on CaymanMarek Olšák2012-09-271-0/+5
| | | | NOTE: This is a candidate for the stable branches.
* r600g: fix instance divisor on CaymanMarek Olšák2012-09-271-19/+35
| | | | | | Not sure if this is the best way to fix it. NOTE: This is a candidate for the stable branches.
* r600g: flush FMASK and CMASK when changing colorbuffers on EvergreenMarek Olšák2012-09-276-1/+18
| | | | | | This fixes rare graphical corruption. NOTE: This is a candidate for the stable branches.
* r600g: use invalid DB hardware formats to disable depth/stencilMarek Olšák2012-09-273-2/+23
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* radeon/llvm: improve select_cc lowering to generate CND* more oftenVincent Lejeune2012-09-274-41/+103
| | | | | | | | v2: - Simplify isZero() - Remove a unused function prototype - Clean whitespace trails Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: fix truncated register define.Alex Deucher2012-09-261-3/+3
| | | | Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: move draw cmds to si_commands.cChristian Koenig2012-09-263-14/+35
| | | | | Signed-off-by: Christian Koenig <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: start seperating commands into si_commands.cChristian Koenig2012-09-263-4/+10
| | | | | Signed-off-by: Christian Koenig <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: get rid of evergreen_hw_context.cChristian Koenig2012-09-263-50/+3
| | | | | Signed-off-by: Christian Koenig <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove unused codeChristian Koenig2012-09-261-19/+0
| | | | | Signed-off-by: Christian Koenig <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: start reworking inferred state handlingChristian König2012-09-264-6/+4
| | | | | | | | | | | Instead of tracking the inferred state changes separately just check if queued and emitted states are the same. This patch just reworks the update of the SPI map between vs and ps, but there are probably more cases like this. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium: Add PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE v2Tom Stellard2012-09-251-0/+16
| | | | | | v2: - Add comment in screen.rst - Report OpenCL required minimum for r600g
* r600g: Handle multiple kernels in the same program v2Tom Stellard2012-09-255-21/+84
| | | | | v2: - Use pc parameter of launch_grid
* nv50/ir/ra: Fix register interference tracking.Jay Cornwall2012-09-251-4/+4
| | | | See fdo bug 55224.
* radeon/llvm: Fix instruction encoding for r600 family GPUsTom Stellard2012-09-243-15/+14
| | | | | | Tested-by: Michel Dänzer <[email protected]> https://bugs.freedesktop.org/show_bug.cgi?id=55217
* r600g: Set RADEON_FLUSH_KEEP_TILING_FLAGS when emitting compute csTom Stellard2012-09-241-1/+7
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* radeon/llvm: support for interpolation intrinsicsVincent Lejeune2012-09-2210-2/+318
| | | | Reviewed-by: Tom Stellard <[email protected]>
* r600g: Fix build with LLVM compilerTom Stellard2012-09-211-1/+1
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* r600g: set QUANT_MODE on Cayman tooMarek Olšák2012-09-221-1/+2
| | | | | | This fixes piglit/fbo-blit-stretched. Reviewed-by: Alex Deucher <[email protected]>
* r600g: use CS helpers to emit streamout stateMarek Olšák2012-09-222-33/+14
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: remove initialization of unused loop register tablesMarek Olšák2012-09-222-38/+0
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: remove now-unused SURFACE_BASE_UPDATE logicMarek Olšák2012-09-223-9/+3
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: remove unused CB registers from register listsMarek Olšák2012-09-222-87/+0
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: atomize framebuffer stateMarek Olšák2012-09-2211-868/+664
| | | | | | Tested on RS880, Evergreen and Cayman. Reviewed-by: Alex Deucher <[email protected]>
* r600g: don't snoop context state while building shadersMarek Olšák2012-09-223-28/+43
| | | | | | Let's use the shader key describing the state. Reviewed-by: Alex Deucher <[email protected]>
* radeon/llvm: Handle loads from the constants address space.Tom Stellard2012-09-212-0/+10
| | | | | Reading from constant memory is not supported yet, so constant reads use global memory.
* radeon/llvm: Add support for v4f32 stores on R600Tom Stellard2012-09-213-9/+27
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* radeon/llvm: Add support for i8 reads on R600Tom Stellard2012-09-213-0/+25
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* radeon/llvm: Expand vector fadd and fmul on R600Tom Stellard2012-09-211-0/+3
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* radeon/llvm: Add optimization for FP_ROUNDTom Stellard2012-09-212-0/+27
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* radeon/llvm: Replace AMDGPU pow intrinsic with the llvm versionTom Stellard2012-09-214-7/+26
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* llvmpipe: fix overflow bug in total texture size computationBrian Paul2012-09-201-2/+16
| | | | | | | | | | | | | | | | v2: use uint64_t for the total_size variable, per Jose. Also add two earlier checks for exceeding the max texture size. For example a 1K^3 RGBA volume would overflow the lpr->image_stride variable. Use simple algebra to avoid overflow in intermediate values. So instead of "x * y > z" use "x > z / y". This should work if we happen to be on a platform that doesn't have 64-bit types. Reviewed-by: Jose Fonseca <[email protected]>
* r600g/llvm: rs780/rs880 are r600 asicsAlex Deucher2012-09-201-2/+2
| | | | Signed-off-by: Alex Deucher <[email protected]>
* r300/compiler: Use precomputed q values in the register allocatorTom Stellard2012-09-191-1/+69
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* r300g: Init regalloc state during context creationTom Stellard2012-09-198-155/+204
| | | | | | Initializing the regalloc state is expensive, and since it is always the same for every compile we only need to initialize it once per context. This should help improve shader compile times for the driver.
* r300/compiler: Don't create register classes for inputsTom Stellard2012-09-191-14/+1
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* ra: Add q_values parameter to ra_set_finalize()Tom Stellard2012-09-191-1/+1
| | | | | | This allows the user to pass precomputed q values to the allocator. Reviewed-by: Kenneth Graunke <[email protected]>
* r600g: Invalidate texture cache when creating vertex buffers for compute v2Tom Stellard2012-09-191-1/+3
| | | | | | | | | | | Compute shaders fetch data from vertex buffers via the texture cache, so we need to make sure the texture cache is flushed. v2: - Fix rebase mistake - Fix spelling in comment Reviewed-by: Marek Olšák <[email protected]>
* r600g: Use LOOP_START_DX10 for loopsTom Stellard2012-09-193-2/+11
| | | | | | | | | | LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not limited to 4096 iterations like the other LOOP_* instructions. Compute shaders need to use this instruction, and since we aren't optimizing loops with the LOOP_CONFIG* registers for pixel and vertex shaders, it seems like we should just use it for everything. Reviewed-by: Marek Olšák <[email protected]>
* r600g: Set the correct value of COLOR*_DIM for RATsTom Stellard2012-09-191-2/+2
| | | | | | | | | For buffers (which is what is being used for RATs), the COLOR*_DIM.WIDTH_MASK field needs to be set to the low 16-bits of the buffer size, and the COLOR*_DIM.HEIEGHT_MAX needs to be set to the high bits. Reviewed-by: Marek Olšák <[email protected]>
* r600g: Make sure to initialize DB_DEPTH_CONTROL register for computeTom Stellard2012-09-191-1/+3
| | | | | | The kernel CS checker will fail if this register is not initialized. Reviewed-by: Marek Olšák <[email protected]>
* r600g: Add some comments and debug printfs to compute codeTom Stellard2012-09-192-5/+53
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g: Add missing break to case statementTom Stellard2012-09-191-0/+1
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* radeon/llvm: Emit ISA for ALU instructions in the R600 code emitterMichal Sciubidlo2012-09-1910-167/+359
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Only support 512 constant registers on R600Tom Stellard2012-09-191-1/+1
| | | | | This is necessary upcoming encoding changes, since we will only be using 9-bits for register encoding.
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