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* radeon/llvm: Match fexp2 for SI.Michel Dänzer2012-09-071-1/+3
| | | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g: order atom emission v3Jerome Glisse2012-09-067-82/+116
| | | | | | | | | | | | | To avoid GPU lockup registers must be emited in a specific order (no kidding ...). This patch rework atom emission so order in which atom are emited in respect to each other is always the same. We don't have any informations on what is the correct order so order will need to be infered from fglrx command stream. v2: add comment warning that atom order should not be taken lightly v3: rebase on top of alphatest atom fix Signed-off-by: Jerome Glisse <[email protected]>
* r600g: fix num of dwords needed for alphatest_state atomJerome Glisse2012-09-061-1/+1
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* llvmpipe: Make driver name more informative.José Fonseca2012-09-061-1/+4
| | | | | | | | | | | | | | | Such as "llvmpipe (LLVM 3.1, 128 bits)" or "llvmpipe (LLVM 3.1, 256 bits)" when leveraging AVX 8-wide registers. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi: Handle more L/I/A format cases.Michel Dänzer2012-09-061-0/+14
| | | | | | | Fixes piglit fbo-generatemipmap-formats. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Enable whole quad mode for pixel shaders.Michel Dänzer2012-09-061-2/+10
| | | | | | | Fixes wrong mipmap level being sampled at some triangle edges. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Add intrinsic for enabling whole quad mode in SI pixel shaders.Michel Dänzer2012-09-064-0/+23
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: SI shader vector instructions implicitly use the EXEC register.Michel Dänzer2012-09-061-0/+4
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Extend SI EXEC register support.Michel Dänzer2012-09-062-2/+7
| | | | | | | Add 32 bit lo and hi variants, and binary encodings. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Remove R600InstrInfo.td from TD_FILESTom Stellard2012-09-061-1/+0
| | | | | Fixes build bug introduced by cebbdd4ac23725963207bf6f8fc7101150e6065f
* radeonsi: Enable NPOT textures again.Michel Dänzer2012-09-061-1/+1
| | | | | | | | Should be at least mostly working now (with the corresponding fixes in libdrm_radeon). Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: Mipmaps require memory footprint to be padded to powers of two.Michel Dänzer2012-09-061-0/+1
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: Sampler view state simplification.Michel Dänzer2012-09-061-11/+9
| | | | | | | | We can always use the offset and tiling mode from level 0 and restrict the first and last mipmap level to be used in the sampler resource. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: Untiled textures are linear aligned, not linear general.Michel Dänzer2012-09-061-3/+3
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/llvm: Cleanup makefileTom Stellard2012-09-062-13/+37
| | | | | Hopefully, this will fix all the parallel make problems people have been having.
* Remove useless checks for NULL before freeingMatt Turner2012-09-0510-43/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Same as earlier commit, except for "FREE" This patch has been generated by the following Coccinelle semantic patch: // Remove useless checks for NULL before freeing // // free (NULL) is a no-op, so there is no need to avoid it @@ expression E; @@ + FREE (E); + E = NULL; - if (unlikely (E != NULL)) { - FREE(E); ( - E = NULL; | - E = 0; ) ... - } @@ expression E; type T; @@ + FREE ((T) E); + E = NULL; - if (unlikely (E != NULL)) { - FREE((T) E); ( - E = NULL; | - E = 0; ) ... - } @@ expression E; @@ + FREE (E); - if (unlikely (E != NULL)) { - FREE (E); - } @@ expression E; type T; @@ + FREE ((T) E); - if (unlikely (E != NULL)) { - FREE ((T) E); - } Reviewed-by: Brian Paul <[email protected]>
* Remove useless checks for NULL before freeingMatt Turner2012-09-051-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch has been generated by the following Coccinelle semantic patch: // Remove useless checks for NULL before freeing // // free (NULL) is a no-op, so there is no need to avoid it @@ expression E; @@ + free (E); + E = NULL; - if (unlikely (E != NULL)) { - free(E); ( - E = NULL; | - E = 0; ) ... - } @@ expression E; type T; @@ + free ((T) E); + E = NULL; - if (unlikely (E != NULL)) { - free((T) E); ( - E = NULL; | - E = 0; ) ... - } @@ expression E; @@ + free (E); - if (unlikely (E != NULL)) { - free (E); - } @@ expression E; type T; @@ + free ((T) E); - if (unlikely (E != NULL)) { - free ((T) E); - } Reviewed-by: Brian Paul <[email protected]>
* Don't cast the return value of malloc/reallocMatt Turner2012-09-054-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch has been generated by the following Coccinelle semantic patch: // Don't cast the return value of malloc/realloc. // // Casting the return value of malloc/realloc only stands to hide // errors. @@ type T; expression E1, E2; @@ - (T) ( _mesa_align_calloc(E1, E2) | _mesa_align_malloc(E1, E2) | calloc(E1, E2) | malloc(E1) | realloc(E1, E2) )
* radeon/llvm: Fix operand ordering for V_CNDMASK_B32Tom Stellard2012-09-051-3/+3
| | | | This fixes several hundred piglit tests.
* radeon/llvm: Use correct float->int conversion opcode on SI.Tom Stellard2012-09-051-2/+4
| | | | | V_CVT_I32_F32 converts floats to signed integers, but we were using V_CVT_F32_I32 which convertes signed integers to float.
* radeon/llvm: Fix lowering of SI_V_CNDLTTom Stellard2012-09-041-3/+3
| | | | | SREG_LIT_0 is a scalar register, so it can only be used in the first argument of vector instructoins.
* radeon/llvm: Fix encoding of V_CNDMASK_B32Tom Stellard2012-09-042-4/+4
| | | | | | | The CodeEmitter was not setting the VGPR bit for src0, because the instruction definition had the VCC register in the src0 slot, instead of the actual src0 register. This has been fixed by moving the VCC register to the end of the operand list.
* radeon/llvm: do not convert f32 operand of select_cc nodeVincent Lejeune2012-09-041-20/+20
| | | | | | v2:-use camel coding style Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 (bool)Vincent Lejeune2012-09-042-2/+26
| | | | | | v2:-wrap line at 80 characters Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: support setcc on f32Vincent Lejeune2012-09-041-9/+27
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radon/llvm: br_cc f32 now lowered without castVincent Lejeune2012-09-041-9/+24
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: swap wrong OPCODE_IS_*_ZERO_* opcode and useVincent Lejeune2012-09-042-4/+4
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: stop big offsets from hanging the GPU v2Christian König2012-09-041-2/+9
| | | | | | | v2: rebased of radeon/llvm fix. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: adjust PIPE_SHADER_CAP_MAX_CONSTSChristian König2012-09-042-5/+2
| | | | | | | So it matches what we really can do. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: fix SelectADDR8BitOffsetChristian König2012-09-041-1/+1
| | | | | | | The offset is unsigned, not signed. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* r600g: adjust QUANT_MODE for higher precisionVadim Girlin2012-09-044-2/+24
| | | | | | | | | Use 1/256 for R6xx/7xx, 1/4096 for evergreen, instead of default 1/16. Helps to pass some piglit tests (fbo, multisample). Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: disable array-textures for nowChristian König2012-09-031-1/+1
| | | | Signed-off-by: Christian König <[email protected]>
* radeonsi: disable Z16 for nowChristian König2012-09-031-2/+2
| | | | | | | It's causing crashes. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: disable NPOT textures for nowChristian König2012-09-031-1/+1
| | | | | | | | | Looks like we have an alignment issue with NPOT textures and mipmaps. So disable NPOT textures until we figure out what is going wrong here. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: handle indirect constants gracefullyChristian König2012-09-031-0/+7
| | | | | | | It's not supported yet, so at least don't try to crash the box. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/llvm: Rework how immediate operands are handled with SITom Stellard2012-08-3110-44/+150
| | | | | | | Immediate operands were previously handled in the CodeEmitter, but that code was buggy and very confusing. This commit adds a pass that simplifies the handling of immediate operands by spliting the loading of the immediate into a sperate insruction that is bundled with the original.
* radeon/llvm: Fix typo in assertTom Stellard2012-08-311-1/+1
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* radeon/llvm: Fix isEG tablegen predicateTom Stellard2012-08-311-3/+5
| | | | | This predicate incorrectly included SI GPUs, so some Evergreen instructions were being emmitted on SI.
* radeon/llvm: Add support for RCP instruction on SITom Stellard2012-08-311-1/+3
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* radeon/llvm: Support AMDGPUfmin DAG node on SITom Stellard2012-08-311-1/+3
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* radeonsi: Handle TGSI_SEMANTIC_PSIZETom Stellard2012-08-311-0/+1
| | | | | | | | | | The relevant POINT_SIZE registers are being set using the pipe_rasterizer_state, so we just need to tell the shader compiler which export type to use. This fixes several of the glean glsl tests. Reviewed-by: Alex Deucher <[email protected]>
* r600g: enable transform feedback on CaymanMarek Olšák2012-08-311-3/+1
| | | | There doesn't seem to be anything wrong with it.
* r600g: implement MSAA for CaymanMarek Olšák2012-08-316-72/+184
| | | | | Everything works except for blitting MSAA colorbuffers, which isn't so trivial on Cayman. It's a rarely-used feature anyway.
* r600g: enable MSAA on r6xx by defaultMarek Olšák2012-08-301-3/+6
| | | | | DRM 2.22.0 is required though. Also require the new DRM for r700, as there are some important fixes for that generation too.
* r600g: disable MSAA depth decompression on r6xxMarek Olšák2012-08-301-1/+10
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* r600g: implement color resolve for r600Marek Olšák2012-08-307-26/+199
| | | | | | | | | The blend state is different and the resolve single-sample buffer must have FMASK and CMASK enabled. I decided to have one CMASK and one FMASK per context instead of per resource. There are new FMASK and CMASK allocation helpers and a new buffer_create helper for that.
* r600g: fix CB_SHADER_MASK and CB_TARGET_MASK for r6xxMarek Olšák2012-08-301-11/+24
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* r600g: implement draw_rectangle callbackMarek Olšák2012-08-303-2/+72
| | | | | | The color resolve on r6xx needs PT_RECTLIST. Using conventional primitive types (triangles and quads) produces an ugly line between two diagonally opposite corners. I guess a rectangular point sprite would work too.
* r600g: implement MSAA for r700Marek Olšák2012-08-307-41/+262
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: change programming of CB_SHADER_MASK on r600-r700Marek Olšák2012-08-301-1/+2
| | | | | | | This one actually makes more sense and gives the expected value for MSAA resolve. Reviewed-by: Jerome Glisse <[email protected]>
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