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* radeonsi: add samplemask parameter to si_export_mrt_colorMarek Olšák2016-02-211-3/+7
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add start_instance parameter to get_instance_index_for_fetchMarek Olšák2016-02-211-4/+6
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: separate out shader key bits for prologs & epilogsMarek Olšák2016-02-214-100/+140
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: compute how many input VGPRs fragment shaders haveMarek Olšák2016-02-212-0/+43
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: compute how many input SGPRs and VGPRs shaders haveMarek Olšák2016-02-212-0/+34
| | | | | | | Prologs (shader binaries inserted before the API shader binary) need to know this, so that they won't change the input registers unintentionally. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add basic code for setting shader return valuesMarek Olšák2016-02-214-8/+21
| | | | | | LLVMBuildInsertValue will be used on return_value. Reviewed-by: Nicolai Hähnle <[email protected]>
* nvc0: enable compute shaders on FermiSamuel Pitoiset2016-02-211-1/+3
| | | | | | | | Kepler compute support is really different than Fermi and it's not ready yet. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: add atomics support on shared memory for FermiSamuel Pitoiset2016-02-212-2/+102
| | | | | | | | | | | | | | Changes from v3: - move the previous OP_SELP change to the previous commit Changes from v2: - make sure the op is OP_SELP when emitting the predicate and add one assert - use bld.getSSA() for mkOp2() - add cross edge between tryLockAndSetBB and joinBB Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nv50/ir: make OP_SELP a compare instructionSamuel Pitoiset2016-02-213-10/+19
| | | | | | | | | | This OP_SELP insn will be used to handle compare and swap subops. Changes from v2: - fix logic for GK110+ Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: add lock/unlock subops for load/storeSamuel Pitoiset2016-02-213-2/+26
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: use s[] addr space for shared buffersSamuel Pitoiset2016-02-211-11/+30
| | | | | | | | | | | | Shared memory address space (FILE_MEMORY_SHARED) must be used instead of global memory when a shared memory area is declared. Changes from v2: - oops, do not remove TGSI_FILE_BUFFER in a switch in nv50_ir_from_tgsi.cpp Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: reduce likelihood of collision for real buffers on FermiSamuel Pitoiset2016-02-211-2/+2
| | | | | | | | | | | Reduce likelihood of collision with real buffers by placing the hole at the top of the 4G area. This fixes some indirect draw+compute tests with large buffers. Suggested by Ilia Mirkin. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: invalidate compute state when switching pipe contextsSamuel Pitoiset2016-02-211-1/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: add support for indirect compute on FermiSamuel Pitoiset2016-02-216-20/+81
| | | | | | | | | | | | When indirect compute is used, the size of the grid (in blocks) is stored as three integers inside a buffer. This requires a macro to set up GRIDDIM_YX and GRIDDIM_Z. Changes from v2: - do not launch the grid if the number of groups for a dimension is 0 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: bind textures/samplers for compute on FermiSamuel Pitoiset2016-02-213-8/+57
| | | | | | | | | | | Textures and samplers don't seem to be aliased between COMPUTE and 3D. Changes from v2: - refactor the code to share (almost) the same logic between 3d and compute Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: bind shader buffers for compute on FermiSamuel Pitoiset2016-02-215-7/+56
| | | | | | | | This is loosely based on 3D. Shader buffers are bound on c15 (the driver constbuf) at offset 0x200. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: bind driver constbuf for compute on FermiSamuel Pitoiset2016-02-215-0/+29
| | | | | | | | | | | Changes from v3: - add new validation state for COMPUTE driver constbuf Changes from v2: - always bind the driver consts even if user params come in via clover Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: add a new validation state for 3D driver constbufSamuel Pitoiset2016-02-212-0/+19
| | | | | | | | | This will be used to invalidate 3D driver constbuf when using COMPUTE and vice-versa. This is needed because this CB contains a bunch of useful information like the addrs of shader buffers. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: bind constant buffers for compute on FermiSamuel Pitoiset2016-02-215-13/+81
| | | | | | | | | | | | | | | Loosely based on 3D. Changs from v3: - invalidate COMPUTE CBs after validating 3D CBs because they are aliased Changes from v2: - get rid of the 's' param to nvc0_cb_bo_push() because it doesn't matter to upload constbufs for compute using the 3d chan Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: allocate an area for compute user constbufsSamuel Pitoiset2016-02-214-18/+20
| | | | | | | For compute shaders, we might need to upload uniforms. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50: do not advertise about compute shadersSamuel Pitoiset2016-02-201-1/+1
| | | | | | | | | Compute shaders are totally unsupported. This avoids Clover to report that OpenCL is supported on Tesla because it's a lie. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Pierre Moreau <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* llvmpipe: add a few const qualifiersBrian Paul2016-02-193-4/+4
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* trace: assorted whitespace and formatting fixesBrian Paul2016-02-191-29/+31
| | | | Reviewed-by: Eduardo Lima Mitev <[email protected]>
* trace: remove unneeded inline qualifiersBrian Paul2016-02-191-46/+46
| | | | Reviewed-by: Eduardo Lima Mitev <[email protected]>
* svga: allow non-contiguous VS input declarationsBrian Paul2016-02-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | This fixes a glDrawPixels regression since b63fe0552b5f. The new quad-drawing utility code uses 3 vertex attributes (xyz, rgba, st). For glDrawPixels path we don't use the rgba attribute so there's a gap in the TGSI VS input declarations (INPUT[0] = pos, INPUT[2] = texcoord). The TGSI->VGPU10 translations code did not handle this correctly. I missed this because my VM was configured for HWv11 while testing. Another way to fix this would be to change the tgsi_scan.c code so that the tgsi_shader_info::num_inputs (and num_outputs) included the unused inputs/outputs. These counts would then actually be "max input register index + 1" rather than "number of used inputs". But that change could impact all drivers so put it off for now. No regressions found with piglit or typical GL apps. v2: also update alloc_system_value_index() to use info.file_max[] Reviewed-by: Charmaine Lee <[email protected]>
* trace: fix new gcc6 warningsRob Clark2016-02-181-7/+0
| | | | | | | | | | | | | | | | src/gallium/drivers/trace/tr_context.c:1713:39: warning: ‘rbug_blocker_flags’ defined but not used [-Wunused-const-variable] static const struct debug_named_value rbug_blocker_flags[] = { ^~~~~~~~~~~~~~~~~~ Note that use of rbug_blocker_flags was removed in: commit 5494332128da0b2826e85df5eeaa878bb5c30a4e Author: Jakob Bornecrantz <[email protected]> Date: Wed May 12 19:26:19 2010 +0100 trace: Remove rbug from trace Signed-off-by: Rob Clark <[email protected]>
* radeon/llvm: Add TargetLibraryInfo to the pass managerTom Stellard2016-02-171-1/+7
| | | | | | | | This will prevent optimization passes from introducing unsupported library calls. Tested-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon/llvm: Set the target triple on the moduleTom Stellard2016-02-174-4/+12
| | | | | Tested-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nvc0: invalidate all buffers when switching pipe contextsSamuel Pitoiset2016-02-171-0/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* freedreno: expose time-elapsed queryRob Clark2016-02-172-1/+5
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: implement time-elapsed queryRob Clark2016-02-172-0/+133
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: better occlusion/sample countingRob Clark2016-02-171-1/+6
| | | | | | | | | | This seems to give more reliable results. More similar to what we do on a3xx, although I think it breaks the a3xx theory that the four sets of results map to each MRT (since we appear to still only have four sets on a4xx). The divide-by-two is a bit odd, but seems to be needed for some reason. Signed-off-by: Rob Clark <[email protected]>
* freedreno/query: fix refcnt'ing issueRob Clark2016-02-171-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/query: some queries don't have ->begin_query()Rob Clark2016-02-172-0/+18
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/query: align counter snapshot locationsRob Clark2016-02-171-0/+2
| | | | | | | | | | | | Some hw queries need their sample memory locations to have certain alignment. At the moment that isn't an issue, since the only hw query is occlusion, so all samples have the same size. But when others are added with different sample sizes, this starts to be a problem. All current and immediately upcoming hw queries simply need their sample address aligned to their size, so let's use that for now. Signed-off-by: Rob Clark <[email protected]>
* freedreno/query: add optional enable hookRob Clark2016-02-175-0/+36
| | | | | | | | Add enable hook for hw query providers. Some will need to configure perfctr selector registers, which we want to do at the start of the submit. Signed-off-by: Rob Clark <[email protected]>
* freedreno: query max gpu freqRob Clark2016-02-172-0/+11
| | | | | | | | This will be needed to support converting from cycle counts to time for performance related queries (initially time-elapsed, but there are some additional performance counters that could be wired up). Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2016-02-175-30/+1355
| | | | | | Mostly to pull in perf ctrs. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix new gcc6 errorsRob Clark2016-02-171-1/+0
| | | | | | | | | | | | | | | | src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c: In function ‘emit_tex’: src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c:1368:26: warning: unused variable ‘const_off’ [-Wunused-variable] struct ir3_instruction *const_off[4]; ^~~~~~~~~ unused since: commit 8750299a420af76cebd3067f6f603eacde06ae06 Author: Jason Ekstrand <[email protected]> Date: Tue Feb 9 14:51:28 2016 -0800 nir: Remove the const_offset from nir_tex_instr Signed-off-by: Rob Clark <[email protected]>
* nv50/ir: we can't do the add to mad conversion when the mul saturatesKarol Herbst2016-02-161-0/+3
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: optimize neg(and(set, 1)) to setKarol Herbst2016-02-161-0/+32
| | | | | | | | | | | | | | | | | | | helps shaders in saints row IV, bioshock infinite and shadow warrior total instructions in shared programs : 1914931 -> 1903900 (-0.58%) total gprs used in shared programs : 247920 -> 247785 (-0.05%) total local used in shared programs : 5673 -> 5673 (0.00%) total bytes used in shared programs : 17558272 -> 17457320 (-0.57%) local gpr inst bytes helped 0 137 719 719 hurt 0 12 0 0 v2: remove this opt for OP_SLCT and check against float for OP_SET v3: simplified the code Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: fix quadop emission in the presence of predicationIlia Mirkin2016-02-164-5/+9
| | | | | | | | | | | | When there's a predicate, it just goes onto the sources list. If the quadop only has a single regular source, we will end up thinking that the predicate is the second source. Check explicitly for the predSrc so that we don't accidentally emit the wrong thing. This fixes a bunch of dEQP-GLES3.functional.shaders.derivate.* tests. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nv50,nvc0: enable/disable seamless cubemap texturing as requestedIlia Mirkin2016-02-1612-3/+26
| | | | | | | | | | In a situation where the seamless setting isn't available on a per-texture basis (G200+ Teslas, and all Fermis), assume that all samplers will have it identically set, and enable accordingly. This fixes arb_seamless_cubemap piglit test on Fermi and Tesla. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: enable compute support on GK110:GM200 with an envvarSamuel Pitoiset2016-02-161-2/+7
| | | | | | | | | | | | | Without this NVF0_COMPUTE environment variable, compute support is initialized by default and this is not what we want for now because it might break 3D. It will be enabled by default once we are sure it won't break anything. Please note that compute support on GM200+ is not enabled yet because it needs to be double-checked. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: add compute support for GM107Samuel Pitoiset2016-02-162-1/+5
| | | | | | | | Fortunately, compute support on GM107 is very close to GK110, except the GK110_COMPUTE.UNK02C4 which is invalid and should not be used. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: fix compute state initialization on GK110+Samuel Pitoiset2016-02-161-6/+7
| | | | | | | | | | | Because our firmware doesn't support the GK110_COMPUTE.FIRMWARE[0x6] method the GPU hangs when it is used. Removing it fix the issue and allow to launch compute shaders on GK110+. Tested on GK208 and GM107. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gm107/ir: add ATOM CAS emissionSamuel Pitoiset2016-02-161-15/+27
| | | | | | | | | This fixes the following dEQP test and the other compswap variants. dEQP-GLES31.functional.ssbo.atomic.compswap.highp_int Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* Handle removal of LLVMAddTargetData in SVN revision 260919Matthew Dawson2016-02-161-0/+6
| | | | | | | | | | | | | | | | | | | LLVM removed LLVMAddTargetData for the 3.9 release in r260919. For the two places in mesa where this is called, only enable the lines when compiling for less then 3.9. For the radeon driver, I'm not sure how to check if any other LLVM calls need to be adjusted. I think since the target data used is extracted from the LLVMModule, it isn't necessary to pass it back to LLVM again. The code does compile, and at least for radeonsi does run OpenGL games. [ Michel Dänzer: Move #if closer to LLVMAddTargetData in lp_bld_init.c, and add HAVE_LLVM < 0x0309 guards around now unused occurrences of TD and data_layout ] Signed-off-by: Matthew Dawson <[email protected]> Reviewed-and-Tested-by: Michel Dänzer <[email protected]>
* nvc0: initial support for GM20x GPUsBen Skeggs2016-02-164-0/+10
| | | | | Signed-off-by: Ben Skeggs <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nvc0: implement support for maxwell texture headersBen Skeggs2016-02-163-6/+203
| | | | | | | | | | | | | Adds support for the new TIC layout that's present on Maxwell GPUs, heavily based on the code for the existing layout. This code is required for GM20x support. While GM10x supports the older layout still, this commit switches it to use the updated version instead. Piglit testing shows zero regressions on GM107. Signed-off-by: Ben Skeggs <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
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