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* r600g/sb: fix kcache handling on r6xxVadim Girlin2013-05-071-1/+5
| | | | | | | | | Use the same limit for kcache constants in alu group on r6xx as on other chips (two const pairs). Relaxing this will require additional checks to make sure that all 4 consts in the group come from 2 kcache sets (clause limit), probably without noticeable improvements of shader performance. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/llvm: Parse config values in register / value pairsTom Stellard2013-05-062-4/+31
| | | | Rather than relying on a predetermined order for the config values.
* r600g/llvm: Don't feed LLVM output through r600_bytecode_build()Tom Stellard2013-05-064-395/+21
| | | | | The LLVM backend emits raw ISA now, so we can just its output unmodified.
* r600g/llvm: Don't emit CALL_FS for vertex shadersTom Stellard2013-05-062-8/+10
| | | | The LLVM backend takes care of this now.
* radeon/llvm: Always build libradeonllvm as staticTom Stellard2013-05-063-17/+10
| | | | | | | | | This library is very small, so there is not much to gain from building it as a shared library. Also, when linking statically with LLVM, a shared libradeonllvm exports LLVM symbols and creates problems when used with other shared objects that also link statically to LLVM. Reviewed-by: [email protected]
* radeon/llvm: Use LLVM C API for compiling LLVM IR to ISA v2Tom Stellard2013-05-065-203/+173
| | | | | | | | | | | The LLVM C API is considered stable and should never change, so it is much more desirable to use than the LLVM C++ API, which is constantly in flux. v2: - Split target initialization and lookup into separate functions Reviewed-by: [email protected]
* gallivm: Move LLVMStartMultithreaded() static initializer into gallivmTom Stellard2013-05-061-14/+0
| | | | | | | This does not solve all of the problems with using LLVM in a multithreaded enivronment, but it should help in some cases. Reviewed-by: [email protected]
* radeon/llvm: Don't use the global context when parsing LLVM IRTom Stellard2013-05-061-2/+3
| | | | | | | This leads to crashes when multiple threads try to compile compute shaders in the same time. Fixes a crash in bfgminer when using more than one thread.
* r600g/llvm: Update radeon family mappings for LLVM backendTom Stellard2013-05-062-4/+8
| | | | | New processors were added to the backend to distinguish between GPUs with and without vertex caches.
* android: add ilo to the build systemChia-I Wu2013-05-061-0/+39
| | | | | | | | | It can be selected with BOARD_GPU_DRIVERS := ilo Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* ilo: correctly set return types of sampler messagesChia-I Wu2013-05-052-0/+3
| | | | | Correctly set the types of the temporaries. We do not want type conversions when moving the results to the final destinations.
* r600g/llvm: Undefines unrequired texture coord valuesVincent Lejeune2013-05-041-1/+28
| | | | | This is a port of "r600g:mask unused source components for SAMPLE" patch from Vadim Girlin.
* nvc0: fixup video decoding with 2D_ARRAYMaarten Lankhorst2013-05-042-5/+4
| | | | Signed-off-by: Maarten Lankhorst <[email protected]>
* gallium: fix type of flags in pipe_context::flush()Chia-I Wu2013-05-0419-20/+20
| | | | | | | | | | | | | | | | It should be unsigned, not enum pipe_flush_flags. Fixed a build error: src/gallium/state_trackers/egl/android/native_android.cpp:426:29: error: invalid conversion from 'int' to 'pipe_flush_flags' [-fpermissive] v2: replace all occurrences of enum pipe_flush_flags by unsigned Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Marek Olšák <[email protected]> [olv: document the parameter now that the type is unsigned]
* llvmpipe: get rid of depth swizzling.Roland Scheidegger2013-05-037-273/+414
| | | | | | | | | | | | | | | Eliminating this we no longer need to copy between linear and swizzled layout. This is probably not quite ideal since it's a bit more work for now, could do some optimizations by moving depth testing outside the fragment shader loop (but tricky for early depth test as we don't have neither the mask nor the interpolated z in the right order handy). The large amount of tile/untile code is no longer needed will be deleted in next commit. No piglit regressions. v2: change a forgotten LAYOUT_NONE to LAYOUT_LINEAR. v3: fix (bogus) uninitialized variable warnings, add comments, fix a bad type Reviewed-by: Jose Fonseca <[email protected]>
* r600g: Correctly initialize the shader key, v2Lauri Kasanen2013-05-031-1/+2
| | | | | | | | | | | | | | | | | | | | | Assigning a struct only copies the members - any padding is left as is. Thus this code: struct foo_t foo; foo = bar; leaves the padding of foo intact, ie uninitialized random garbage. This patch fixes constant shader recompiles by initializing the struct to zero. For completeness, memcpy is used to copy the key to the shader struct. NOTE: This is a candidate for the stable branches. Signed-off-by: Lauri Kasanen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Andreas Boll <[email protected]>
* scons: remove nouveau buildAndreas Boll2013-05-034-43/+0
| | | | | | | One build system for linux/unix only drivers should be enough. Additionally the nouveau target was disabled anyway. Acked-by: Jose Fonseca <[email protected]>
* scons: remove radeon buildAndreas Boll2013-05-033-59/+0
| | | | | | | | One build system for linux/unix only drivers should be enough. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48694 Acked-by: Jose Fonseca <[email protected]>
* r600g: don't emit surface_sync after FLUSH_AND_INV_EVENTAlex Deucher2013-05-031-26/+0
| | | | | | | | | | | | | | | | | It shouldn't be needed since the FLUSH_AND_INV_EVENT has already made sure the destination caches are flushed. Additionally, we didn't previously emit the surface_sync until this commit: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5e4c07e7964a3258ed02b530bcdc24c0650204b Emitting them together causes hangs in compute on cayman/TN and hangs in Heaven on evergreen. Note: this patch is a candidate for the 9.1 branch, but requires: http://cgit.freedesktop.org/mesa/mesa/commit/?id=156bcca62c9f4e79e78929f72bc085757f36a65a as well. Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* r600g/sb: zero-initialize bytecode structsVadim Girlin2013-05-032-3/+6
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix constant propagation in gvn passVadim Girlin2013-05-031-1/+2
| | | | | | Fixes the bug that prevented propagation of literals in some cases. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: don't run unnecessary passesVadim Girlin2013-05-031-3/+0
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: silence warnings with gcc 4.8Vadim Girlin2013-05-032-14/+15
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix handling of interference sets in post_schedulerVadim Girlin2013-05-032-8/+8
| | | | | | | | | | | post_scheduler clears interference set for reallocatable values when the value becomes live first time, and then updates it to take into account modified order of operations, but this was not handled properly if the value appears first time as a source in copy operation. Fixes issues with webgl demo: http://madebyevan.com/webgl-water/ Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix allocation of indirectly addressed input arraysVadim Girlin2013-05-034-10/+25
| | | | | | | | | Some inputs may be preloaded into predefined GPRs, so we can't reallocate arrays with such inputs. Fixes issues with webgl demo: http://oos.moxiecode.com/js_webgl/snake/ Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: use hex instead of binary constantsVadim Girlin2013-05-035-15/+15
| | | | | | This should fix build issues with GCC < 4.3 Signed-off-by: Vadim Girlin <[email protected]>
* r600g: use old shader disassembler by defaultVadim Girlin2013-05-034-19/+18
| | | | | | | | | | | | | | New disassembler is not completely isolated yet from further processing in r600g/sb that is not required for printing the dump, so it has higher probability to fail in case of any unexpected features in the bytecode. This patch adds "sbdisasm" flag for R600_DEBUG that allows to use new disassembler in r600g/sb for shader dumps when shader optimization is not enabled. If shader optimization is enabled, new disassembler is used by default. Signed-off-by: Vadim Girlin <[email protected]>
* radeon/uvd: enable interlaced buffers by defaultChristian König2013-05-032-5/+5
| | | | | | Kills tilling on UVD buffers, but we currently don't really need that. Signed-off-by: Christian König <[email protected]>
* vl/idct: fix for commit 7d2f2a0c890b1993532a45c8c392c28950ddc06eChristian König2013-05-032-6/+6
| | | | | | | | We still need the option for handling 3D textures as well. Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=64143 Signed-off-by: Christian König <[email protected]>
* vl/buffers: fix typo in function nameChristian König2013-05-032-6/+6
| | | | Signed-off-by: Christian König <[email protected]>
* radeon/uvd: fix some MPEG4 artifactsChristian König2013-05-031-7/+17
| | | | | | Still not perfect, but a step in the right direction. Signed-off-by: Christian König <[email protected]>
* ilo: use u_reduced_prims_for_vertices()Chia-I Wu2013-05-031-68/+1
| | | | We do not need our own prim_count() anymore.
* r600g: Don't set the dest cache bits on surface sync for ↵Tom Stellard2013-05-021-15/+13
| | | | | | | | | | | | | R600_CONTEXT_FLUSH_AND_INV We are already emitting a EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT packet when this flush flag is set, so flushing the dest caches with a SURFACE_SYNC should not be necessary. The motivation for this change is that emitting a SURFACE_SYNC packet with the CB bits set was causing compute shaders to hang on Cayman. Reviewed-by: Alex Deucher <[email protected]>
* r600g/compute: Fix build error in debug codeTom Stellard2013-05-021-1/+1
| | | | Reviewed-by: Alex Deucher <[email protected]>
* radeon: Fix build with LLVM 3.3Armin K2013-05-021-1/+1
| | | | Reviewed-by: Tom Stellard <[email protected]>
* r600/sb: Fix build failure with non-standard libdrm installation prefixLauri Kasanen2013-05-021-0/+1
| | | | | | Just like radeon/uvd, r600/sb fails to find the libdrm includes. Signed-off-by: Lauri Kasanen <[email protected]>
* radeon/uvd: Fix build failure with non-standard libdrm installation prefixLauri Kasanen2013-05-021-1/+1
| | | | | | | | | | Without this patch, radeon_uvd failed to find the libdrm includes: In file included from radeon_uvd.c:48: ../../winsys/radeon/drm/radeon_winsys.h:44:35: error: libdrm/radeon_surface.h: No such file or directory Signed-off-by: Lauri Kasanen <[email protected]>
* radeon/uvd: fix quant scan order for mpeg2Christian König2013-05-011-2/+6
| | | | Signed-off-by: Christian König <[email protected]>
* vl/buffer: use 2D_ARRAY instead of 3D texturesChristian König2013-05-012-14/+14
| | | | Signed-off-by: Christian König <[email protected]>
* ilo: fix PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERSChia-I Wu2013-05-011-0/+2
| | | | On GEN7+, is->dev.has_gen7_sol_reset is required.
* ilo: enable SO support on GEN7Chia-I Wu2013-05-011-3/+4
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* ilo: reset SO write offsets for new SO targetsChia-I Wu2013-05-011-6/+15
| | | | | When the SO targets are changed and no appending is requested, we need to send SOL_RESET on GEN7+.
* ilo: correctly program SO states for GEN7Chia-I Wu2013-05-011-7/+46
| | | | With the commands supported by GPE, we can finally program the states.
* ilo: implement GEN7 SO GPE functionsChia-I Wu2013-05-013-40/+150
| | | | They were just stubs before.
* ilo: add gen6_pipeline_update_max_svbi()Chia-I Wu2013-05-012-13/+35
| | | | | Move max_svbi calculation to a helper function and make it available for other GENs.
* ilo: expose register indices of OUTs in ilo_shaderChia-I Wu2013-05-014-4/+30
| | | | | pipe_stream_output_info tells us which of OUT[i] needs to be written out. We need the info to map OUT[i] to VUE offset.
* ilo: allow one-off flags to be specified for CPChia-I Wu2013-05-012-0/+15
| | | | It will be used for SOL_RESET on GEN7.
* ilo: fix tiling/size for special-purpose resourcesChia-I Wu2013-05-011-2/+30
| | | | We do not allocate such resources yet though.
* ilo: use UMS layout for render targetsChia-I Wu2013-05-014-19/+117
| | | | | As we do not advertise MSAA support, this change should not make any difference yet.
* ilo: support and prefer compact array spacingChia-I Wu2013-05-014-15/+77
| | | | | There is no reason to waste the memory when the HW can support compact array spacing (ARYSPC_LOD0).
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