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* nv50: dynamically allocate space for shader local storageMarcin Slusarz2012-06-286-25/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes 21 piglit tests: spec/glsl-1.10/execution/variable-indexing/ fs-temp-array-mat4-index-col-row-wr vs-temp-array-mat4-index-col-row-wr vs-temp-array-mat4-index-row-wr spec/glsl-1.20/execution/variable-indexing/ fs-temp-array-mat3-index-col-row-rd fs-temp-array-mat3-index-row-rd fs-temp-array-mat4-col-row-wr fs-temp-array-mat4-index-col-row-rd fs-temp-array-mat4-index-col-row-wr fs-temp-array-mat4-index-row-rd fs-temp-array-mat4-index-row-wr vs-temp-array-mat3-index-col-row-rd vs-temp-array-mat3-index-col-row-wr vs-temp-array-mat3-index-row-rd vs-temp-array-mat3-index-row-wr vs-temp-array-mat4-col-row-wr vs-temp-array-mat4-index-col-row-rd vs-temp-array-mat4-index-col-row-wr vs-temp-array-mat4-index-col-wr vs-temp-array-mat4-index-row-rd vs-temp-array-mat4-index-row-wr vs-temp-array-mat4-index-wr ... and prevents a lot of GPU lockups
* nv50: streamline screen_create error handlingMarcin Slusarz2012-06-281-38/+46
| | | | | Remove macro which changes control flow (it's evil). Make all fail paths print (correct) error message.
* nv50/ir: make colorful ir dump output optionalMarcin Slusarz2012-06-281-5/+17
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* softpipe: fix numFragsEmitted debug codeBrian Paul2012-06-271-0/+7
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* i915g: Implement sRGB texturesStéphane Marchesin2012-06-265-12/+128
| | | | | | | | Since we don't have them in hw we emulate them in the shader. Although not recommended by the spec it is legit. As a side effect we also get GL 2.1. I think this is as far as we can take the i915.
* svga: return 120 for PIPE_CAP_GLSL_FEATURE_LEVELBrian Paul2012-06-261-1/+3
| | | | Reviewed-by: Marek Olšák <[email protected]>
* llvmpipe: return 120 for PIPE_CAP_GLSL_FEATURE_LEVELBrian Paul2012-06-261-1/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g: enable DUAL_EXPORT mode when possible on r6xx/r7xxJerome Glisse2012-06-273-18/+57
| | | | | | | DUAL_EXPORT can be enabled on r6xx/r7xx when all CBs use 16-bit export and there is no depth/stencil export. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: enable DUAL_EXPORT mode when possibleVadim Girlin2012-06-274-6/+55
| | | | | | | | It seems DUAL_EXPORT on evergreen may be enabled when all CBs use 16-bit export mode (EXPORT_4C_16BPC), also there should be at least one CB, and the PS shouldn't export depth/stencil. Signed-off-by: Vadim Girlin <[email protected]>
* r600g: avoid unnecessary shader exports v2Vadim Girlin2012-06-276-28/+41
| | | | | | | | | | | | In some cases TGSI shader has more color outputs than the number of CBs, so it seems we need to limit the number of color exports. This requires different shader variants depending on the nr_cbufs, but on the other hand we are doing less exports, which are very costly. v2: fix various piglit regressions Signed-off-by: Vadim Girlin <[email protected]> Signed-off-by: Jerome Glisse <[email protected]>
* r600g: cache shader variants instead of rebuilding v3Vadim Girlin2012-06-275-94/+217
| | | | | | | | | | | | | | | | | | | Shader variants are stored in the list, the key for lookup is based on the states that require different hw shaders - currently it's rctx->two_side (all gpus) and rctx->nr_cbufs (evergreen/cayman, when writes_all property is set). v2: - use simple list instead of keymap as suggested by Marek on irc - call r600_adjust_gprs from r600_bind_vs_shader for r6xx/r7xx (r600_shader_select isn't used for vertex shaders currently) v3: - fix call to r600_adjust_gprs - do it after updating current shader Improves performance for some apps, e.g. FlightGear - see https://bugs.freedesktop.org/show_bug.cgi?id=50360 Signed-off-by: Vadim Girlin <[email protected]>
* svga: handle missing PIPE_CAP_x queriesBrian Paul2012-06-261-9/+14
| | | | | | And fix incorrect error message for a bad shader type/number. Reviewed-by: Marek Olšák <[email protected]>
* llvmpipe: handle more PIPE_CAP_x queriesBrian Paul2012-06-261-4/+48
| | | | | | | | | As with the previous commit for softpipe. v2: remove 'default' case to get compile-time warning Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* softpipe: handle more PIPE_CAP_x queriesBrian Paul2012-06-261-3/+31
| | | | | | | | | | These all return zero. Add a debug_printf() to catch the default case so we don't accidently mishandle something important in the future. v2: remove 'default' case to get compile-time warning Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* svga: return 1 for PIPE_CAP_MIXED_COLORBUFFER_FORMATSBrian Paul2012-06-261-1/+3
| | | | | | | | | | | This is actually required for GL_ARB_framebuffer_object, but the state tracker doesn't currently check it. Direct3D 9 allows mixed format color buffers with some restrictions. Setting this allows Unigine Heaven 2.5 and 3.0 to run. Tested both on GL and D3D hosts. Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]>
* r600g: don't disable streamout if it hasn't been startedMarek Olšák2012-06-261-1/+1
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* r600g: inline r600_blit_push_depth and use resource_copy_regionMarek Olšák2012-06-253-18/+11
| | | | | We are going to have a separate resource for depth texturing and transfers and this is just a transfer thing.
* r600g: split flushed depth texture creation and flushingMarek Olšák2012-06-255-16/+34
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* llvmpipe: fix the LP_NO_RAST debug optionBrian Paul2012-06-254-24/+22
| | | | | | | | It was only no-oping the clear() function, not actual triangle rasterization. Move the no_rast field from lp_context down into lp_rasterizer so it's accessible where it's needed. Reviewed-by: Jose Fonseca <[email protected]>
* svga: init pointer to NULL to silence MSVC warningBrian Paul2012-06-221-1/+1
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* r600g: Unify SURFACE_SYNC packet emission for 3D and computeTom Stellard2012-06-213-101/+30
| | | | | | Drop the compute specific evergreen_set_buffer_sync() function and instead use the r600_surface_sync_command atom for emitting SURFACE_SYNC packets.
* r600g: Enable reusing of compute stateTom Stellard2012-06-211-6/+9
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* r600g: Fix reading vtx instruction offset from bytestreamTom Stellard2012-06-211-1/+1
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* radeon/llvm: Turn on the BitExtract peephole optimizationTom Stellard2012-06-212-5/+32
| | | | | Thie BitExtract optimization folds a mask and shift operation together into a single instruction (BFE_UINT).
* radeon/llvm: Lower ROTL to BIT_ALIGNTom Stellard2012-06-216-1/+54
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* radeon/llvm: Use the VLIW Scheduler for R600->NITom Stellard2012-06-2112-8/+75
| | | | | | | | | | | | | | | | | | | It's not optimal, but it's better than the register pressure scheduler that was previously being used. The VLIW scheduler currently ignores all the complicated instruction groups restrictions and just tries to fill the instruction groups with as many instructions as possible. Though, it does know enough not to put two trans only instructions in the same group. We are able to ignore the instruction group restrictions in the LLVM backend, because the finalizer in r600_asm.c will fix any illegal instruction groups the backend generates. Enabling the VLIW scheduler improved the run time for a sha1 compute shader by about 50%. I'm not sure what the impact will be for graphics shaders. I tested Lightsmark with the VLIW scheduler enabled and the framerate was about the same, but it might help apps that use really big shaders.
* make: Fold ASM_CFLAGS into DEFINES.Eric Anholt2012-06-213-3/+0
| | | | | | Every place that uses ASM_FLAGS already uses DEFINES. Not including it in DEFINES is just a way to screw up potential users, as I've done several times while working on the build system.
* nv50: fix buffer reuse issuesMarcin Slusarz2012-06-202-0/+18
| | | | | | | | | | 1) We need to insert a barrier between consecutive transform feedback calls. 2) VBO cache needs to be flushed when TFB output is used as VBO draw input. Fixes Piglit test EXT_transform_feedback/immediate-reuse. Thanks to Christoph Bumiller for pointing out bugs in previous versions of this patch.
* llvmpipe: Add vertex id support.Olivier Galibert2012-06-191-1/+4
| | | | | Signed-off-by: Olivier Galibert <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: Simplify and fix system variables fetch.Olivier Galibert2012-06-191-1/+1
| | | | | | | | | | | | | | The system array values concept doesn't really because it expects the system values to be fixed per call, which is wrong for gl_VertexID and iffy for gl_SampleID. So this patch does two things: - kill the array, have emit_fetch_system_value directly pick the values it needs (only gl_InstanceID for now, as the previous code) - correctly handle the expected type in emit_fetch_system_value Signed-off-by: Olivier Galibert <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* softpipe: Offset is not to be applied to the layer parameter of array ↵Olivier Galibert2012-06-191-2/+2
| | | | | | | texture fetches. Signed-off-by: Olivier Galibert <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* r600g: fix z/stencil texture creation v2Jerome Glisse2012-06-191-15/+17
| | | | | | | | | | z or stencil texture should not be created with the z/stencil flags for surface creation as they are intended to be bound as texture. v2: remove broken code Signed-off-by: Jerome Glisse <[email protected]>
* radeon/llvm: Fix CR/LF in Processors.tdTörök Edwin2012-06-191-17/+17
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Fix sin/cos codegen on R700Török Edwin2012-06-191-19/+24
| | | | | | | | | | Based on https://bugs.freedesktop.org/show_bug.cgi?id=50317#c4 Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=50316 https://bugs.freedesktop.org/show_bug.cgi?id=50317 Signed-off-by: Tom Stellard <[email protected]>
* gallium: Add PIPE_CAP_START_INSTANCEFredrik Höglund2012-06-198-0/+8
| | | | Reviewed-by: Brian Paul <[email protected]>
* scons: Do not build svga if using Solaris Studio C compiler.Vinson Lee2012-06-181-0/+4
| | | | | | | | Solaris Studio C compiler does not support anonymous structs and anonymous unions. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radeon/llvm: Update comment in AMDGPU.tdTom Stellard2012-06-181-2/+3
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* radeon/llvm: Remove unused AMDIL TableGen definitonsTom Stellard2012-06-1818-6140/+26
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* radeon/llvm: Eliminate getRegClassFromType() functionTom Stellard2012-06-181-42/+1
| | | | We can use TargetLowering::getRegClassFor() instead.
* radeon/llvm: Remove deadcode from AMDILISelLowering.cppTom Stellard2012-06-184-1687/+0
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* llvmpipe: Implement cylindrical wrapping.James Benton2012-06-183-4/+82
| | | | | | Tested against mesa demos cylwrap and dx9 DCT address.exe which now passes 100%. Signed-off-by: José Fonseca <[email protected]>
* svga: fix synchronization bug between sampler views and surfacesBrian Paul2012-06-181-0/+5
| | | | | | | | | | This fixes a bug where a sampler view was using stale texture/resource data when the texture was modified through a surface (render to texture). Bumping the texture and layer ages triggers sampler view revalidation. Fixes piglit fbo-blit failure. Reviewed-by: José Fonseca <[email protected]>
* r600g: enable streamout by default on r7xx and DRM 2.17.0Marek Olšák2012-06-173-8/+16
| | | | | | Now that it's in Linus's tree. Has anyone had a chance to test streamout on Cayman recently?
* i915g: More ops commute.Stéphane Marchesin2012-06-152-6/+22
| | | | This allows using the optimizations more broadly.
* r600g: fix lockups with streamout on r7xxMarek Olšák2012-06-152-0/+15
| | | | | | | | | This requires the latest streamout kernel patches. Streamout is disabled by default on r7xx, so this patch is safe for regular users. Reviewed-by: Alex Deucher <[email protected]>
* r600g: compute CS space for streamout correctly, add commentsMarek Olšák2012-06-151-6/+7
| | | | | | SET_CONTEXT_REG was not counted in. Reviewed-by: Alex Deucher <[email protected]>
* r600g: set SMX_ACTION_ENA to fix streamout cache flushes on some chipsetsMarek Olšák2012-06-151-1/+2
| | | | | | It helps on R7xx. Reviewed-by: Alex Deucher <[email protected]>
* winsys/radeon: enable IB submission to compute rings v2Christian König2012-06-151-1/+1
| | | | | | | | | | | This allows to submit things to the compute only rings on cayman+ v2: rebased on current master and actually make use of the new flag in evergreen_compute.c Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nv50,nvc0: fix stream output target buffer leakMarcin Slusarz2012-06-142-0/+2
| | | | | It manifests at exit as: "WARNING: destroying GPU memory cache with some buffers still in use"
* nv50: disable stream output before reconfiguring itChristoph Bumiller2012-06-141-2/+2
| | | | If we don't, the GPU will just throw an ILLEGAL_OPERATION error.
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