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src
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gallium
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drivers
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virgl
Commit message (
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Author
Age
Files
Lines
*
gallium: switch boolean -> bool at the interface definitions
Ilia Mirkin
2019-07-22
5
-51
/
+51
*
virgl: fix a sync issue in virgl_buffer_transfer_extend
Chia-I Wu
2019-07-19
1
-62
/
+15
*
virgl: rework virgl_transfer_queue_extend
Chia-I Wu
2019-07-19
3
-25
/
+24
*
virgl: fix virgl_buffer_transfer_extend
Chia-I Wu
2019-07-19
1
-0
/
+1
*
virgl: Set meta data for textures from handle.
Lepton Wu
2019-07-17
1
-0
/
+1
*
gallium: use MAP_DIRECTLY to mean supression of DISCARD in buffer_subdata
Marek Olšák
2019-07-15
1
-4
/
+6
*
gallium: get rid of PIPE_CAP_SM3
Erik Faye-Lund
2019-07-10
1
-1
/
+3
*
virgl: remove virgl_transfer_queue_lists
Chia-I Wu
2019-07-09
2
-36
/
+13
*
virgl: simplify virgl_transfer_queue_extend
Chia-I Wu
2019-07-09
1
-34
/
+5
*
virgl: remove transfer after transfer_write
Chia-I Wu
2019-07-09
1
-2
/
+1
*
virgl: improve virgl_transfer_queue_is_queued
Chia-I Wu
2019-07-09
1
-30
/
+21
*
virgl: fix transfers_intersect for mipmaps
Chia-I Wu
2019-07-09
1
-7
/
+2
*
virgl: fix some false positives in transfers_overlap
Chia-I Wu
2019-07-09
1
-27
/
+86
*
virgl: Hide internal virgl_resource functions
Alexandros Frantzis
2019-07-06
2
-166
/
+157
*
virgl: Use virgl_resource_transfer_map for textures
Alexandros Frantzis
2019-07-06
2
-60
/
+4
*
virgl: Use virgl_resource_transfer_map for buffers
Alexandros Frantzis
2019-07-06
1
-79
/
+1
*
virgl: Introduce virgl_resource_transfer_map
Alexandros Frantzis
2019-07-06
2
-0
/
+92
*
virgl: Clear the valid buffer range when possible
Alexandros Frantzis
2019-07-03
2
-0
/
+24
*
android: virgl: fix generated virgl_driinfo.h building rules
Mauro Rossi
2019-06-29
1
-2
/
+8
*
virgl: Don't allow creating staging pipe_resources
Alexandros Frantzis
2019-06-28
3
-24
/
+8
*
virgl: Use virgl_staging_mgr
Alexandros Frantzis
2019-06-28
6
-57
/
+34
*
virgl: Add tests for virgl_staging_mgr
Alexandros Frantzis
2019-06-28
3
-0
/
+424
*
virgl: Introduce virgl_staging_mgr
Alexandros Frantzis
2019-06-28
4
-0
/
+230
*
virgl: Store the virgl_hw_res for copy transfers
Alexandros Frantzis
2019-06-28
6
-10
/
+19
*
virgl: add VIRGL_DEBUG_XFER
Chia-I Wu
2019-06-25
3
-4
/
+9
*
virgl: add VIRGL_DEBUG_SYNC
Chia-I Wu
2019-06-25
3
-1
/
+20
*
virgl: fix the value of VIRGL_DEBUG_BGRA_DEST_SWIZZLE
Chia-I Wu
2019-06-25
2
-8
/
+10
*
android: virgl: fix libmesa_winsys_virgil_common build and dependencies
Mauro Rossi
2019-06-21
1
-1
/
+1
*
virgl: Add debug flag to bypass driconf to enable the BGRA tweaks
Gert Wollny
2019-06-20
2
-0
/
+8
*
virgl: Add a tweak to set the value for emulated queries of GL_SAMPLES_PASSED
Gert Wollny
2019-06-20
5
-1
/
+12
*
virgl: Add tweak to apply a swizzle when drawing/blitting to a emulated BGRA ...
Gert Wollny
2019-06-20
5
-0
/
+9
*
virgl: Add driconf tweak for emulating BGRA surfaces on GLES
Gert Wollny
2019-06-20
3
-0
/
+10
*
virgl: Add override for BGRA format to use swizzled SRGB format
Gert Wollny
2019-06-20
4
-1
/
+27
*
virgl: Add code to accept BGRx_SRGB as RGBx_SRGB
Gert Wollny
2019-06-20
2
-3
/
+23
*
virgl: Add skeleton to evaluate cap and send tweaks
Gert Wollny
2019-06-20
5
-0
/
+31
*
virgl: factor out format host bits check
Gert Wollny
2019-06-20
1
-16
/
+17
*
gallium/virgl: Add code path for virgl to read driconf
Gert Wollny
2019-06-20
2
-2
/
+3
*
virgl: Add driinfo file and tie it into the build
Gert Wollny
2019-06-20
3
-2
/
+36
*
virgl: Support VIRGL_BIND_SHARED
David Riley
2019-06-19
2
-0
/
+3
*
virgl: fix sync issue regarding discard/unsync transfers
Chia-I Wu
2019-06-18
1
-5
/
+15
*
virgl_hw: add YUV support
Gurchetan Singh
2019-06-18
1
-0
/
+6
*
virgl: sync to virglrenderer virgl_hw.h
Gurchetan Singh
2019-06-18
1
-3
/
+10
*
virgl: Assume sRGB write control for older guest kernels or virglrenderer hosts
Gert Wollny
2019-06-17
1
-1
/
+2
*
virgl: better support for PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
Chia-I Wu
2019-06-17
4
-25
/
+92
*
virgl: add virgl_rebind_resource
Chia-I Wu
2019-06-17
4
-0
/
+148
*
virgl: save virgl_hw_res in virgl_transfer
Chia-I Wu
2019-06-17
5
-14
/
+22
*
virgl: add resource_reference to virgl_winsys
Chia-I Wu
2019-06-17
2
-2
/
+4
*
virgl: virgl_transfer should own its virgl_resource
Chia-I Wu
2019-06-12
2
-8
/
+6
*
virgl: pass virgl_context to transfer create/destroy
Chia-I Wu
2019-06-12
5
-22
/
+21
*
virgl: init transfer queue from virgl_context
Chia-I Wu
2019-06-12
3
-10
/
+11
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