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* virgl: Remove formats with unusual sample count.Lepton Wu2019-10-241-0/+3
| | | | | | | | | Most GPU require the sample count is power of 2. Just remove those formats with unusual sample count. This decreases dEQP EGL tests run time a lot. Signed-off-by: Lepton Wu <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium: remove PIPE_SHADER_CAP_SCALAR_ISAMarek Olšák2019-10-101-2/+0
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: add PIPE_RESOURCE_FLAG_SINGLE_THREAD_USE to skip util_range lockMarek Olšák2019-10-076-9/+9
| | | | | | | | | u_upload_mgr sets it, so that util_range_add can skip the lock. The time spent in tc_transfer_flush_region decreases from 0.8% to 0.2% in torcs on radeonsi. Reviewed-by: Kenneth Graunke <[email protected]>
* virgl: modify internal structures to track winsys-supplied dataGurchetan Singh2019-10-022-43/+52
| | | | | | | | | | | | | The winsys might supply dimensions that are different than those we calculate. In additional, it may supply virtualized modifiers. In practice, a stride != bpp * width and virtualized modifiers don't happen yet, but the plan is to move in that direction. Also make virgl_resource_layout static. Reviewed by: Robert Tarasov <[email protected]>
* virgl: modify resource_create_from_handle(..) callbackGurchetan Singh2019-10-022-2/+13
| | | | | | | This commit makes no functional changes, just adds the revelant plumbing. Reviewed by: Robert Tarasov <[email protected]>
* virgl: Fix pipe_resource leaks under multi-sample.Lepton Wu2019-09-101-1/+3
| | | | | | | Fixes: 900a80f9e4f ("virgl: virgl_transfer should own its virgl_resource") Signed-off-by: Lepton Wu <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* virgl: fix format conversion for recent gallium changes.Dave Airlie2019-08-266-16/+303
| | | | | | | | | | | | | | | | | | The virgl formats are fixed in time snapshots of the gallium ones, we just need to provide a translation table between them when we enter the hardware. This fixes a regression since Eric renumbered the gallium table. Fixes: c45c33a5a2 (gallium: Remove manual defining of PIPE_FORMAT enum values.) Bugzilla: https://bugs.freedesktop.org/111454 v1 by Dave Airlie <[email protected]> v2: virgl: Add a number of formats to the table that are used, e.g. for vertex attributes v3: cover some more missing formats from a piglit run Signed-off-by: Gert Wollny <[email protected]>
* virgl: check scanout maskGurchetan Singh2019-08-082-0/+7
| | | | | | | | | Otherwise, virgl will report renderable or texturable formats as also scan-out formats. v2: drop host feature check (@kusma) Reviewed-by: Erik Faye-Lund <[email protected]>
* virgl: fixup_readback_format --> fixup_formatsGurchetan Singh2019-08-081-8/+7
| | | | | | | This function is generalizable. Suggested-by: Erik Faye-Lund <[email protected]> Reviewed-by: Erik Faye-Lund <[email protected]>
* virgl: access caps in a less verbose way in virgl_is_format_supportedGurchetan Singh2019-08-081-9/+9
| | | | Reviewed-by: Erik Faye-Lund <[email protected]>
* virgl: Enable depth_clamp by lowering if the host is new enough.Gert Wollny2019-08-012-1/+8
| | | | | Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Reviewed-by: Marek Olšák <[email protected]>
* virgl: make use of local variableEric Engestrom2019-07-311-1/+1
| | | | | | | | Otherwise that variable is only used in an assert() and would need an ASSERTED to avoid the warning. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* tree-wide: replace MAYBE_UNUSED with ASSERTEDEric Engestrom2019-07-311-1/+1
| | | | | | Suggested-by: Jason Ekstrand <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* gallium: switch boolean -> bool at the interface definitionsIlia Mirkin2019-07-225-51/+51
| | | | | | | | | | | | | | | | | | This is a relatively minimal change to adjust all the gallium interfaces to use bool instead of boolean. I tried to avoid making unrelated changes inside of drivers to flip boolean -> bool to reduce the risk of regressions (the compiler will much more easily allow "dirty" values inside a char-based boolean than a C99 _Bool). This has been build-tested on amd64 with: Gallium drivers: nouveau r300 r600 radeonsi freedreno swrast etnaviv v3d vc4 i915 svga virgl swr panfrost iris lima kmsro Gallium st: mesa xa xvmc xvmc vdpau va Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Acked-by: Alyssa Rosenzweig <[email protected]>
* virgl: fix a sync issue in virgl_buffer_transfer_extendChia-I Wu2019-07-191-62/+15
| | | | | | | | | | | | | | | | | | | | | | | | | In virgl_buffer_transfer_extend, when no flush is needed, it tries to extend a previously queued transfer instead if it can find one. Comparing to virgl_resource_transfer_prepare, it fails to check if the resource is busy. The existence of a previously queued transfer normally implies that the resource is not busy, maybe except for when the transfer is PIPE_TRANSFER_UNSYNCHRONIZED. Rather than burdening us with a lengthy comment, and potential concerns over breaking it as the transfer code evolves, this commit makes the valid_buffer_range check the only condition to take the fast path. In real world, we hit the fast path almost only because of the valid_buffer_range check. In micro benchmarks, the condition should always be true, otherwise the benchmarks are not very representative of meaningful workloads. I think this fix is justified. The recent change to PIPE_TRANSFER_MAP_DIRECTLY usage disables the fast path. This commit re-enables it as well. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: rework virgl_transfer_queue_extendChia-I Wu2019-07-193-25/+24
| | | | | | | | Do not take a transfer and do the memcpy. Add a _buffer suffix to the function name to make it clear that it is only for buffers. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: fix virgl_buffer_transfer_extendChia-I Wu2019-07-191-0/+1
| | | | | | | | Without setting hw_res, virgl_transfer_queue_extend never finds a match and always returns NULL. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: Set meta data for textures from handle.Lepton Wu2019-07-171-0/+1
| | | | | | | | | | The set of meta data was removed by commit 8083464. It broke lots of dEQP tests when running with pbuffer surface type. Fixes: 80834640137 ("virgl: remove dead code") Signed-off-by: Lepton Wu <[email protected]> Reviewed-by: Erik Faye-Lund <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* gallium: use MAP_DIRECTLY to mean supression of DISCARD in buffer_subdataMarek Olšák2019-07-151-4/+6
| | | | | This is needed to fix an issue with OpenGL when a buffer is mapped and BufferSubData is called. In this case, we can't invalidate the buffer range.
* gallium: get rid of PIPE_CAP_SM3Erik Faye-Lund2019-07-101-1/+3
| | | | | | | | | | | | | | | | | | | | | PIPE_CAP_SM3 has always been an odd one out of all our caps. While most other caps are fine-grained and single-purpose, this cap encode several features in one. And since OpenGL cares more about single features, it'd be nice to get rid of this one. As it turns, this is now relatively simple. We only really care about three features using this cap, and those already got their own caps. So we can remove it, and make sure all current drivers just give the same response to all of them. The only place we *really* care about SM3 is in nine, and there we can instead just re-construct the information based on the finer-grained caps. This avoids DX9 semantics from needlessly leaking into all of the drivers, most of who doesn't care a whole lot about DX9 specifically. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Acked-by: Alyssa Rosenzweig <[email protected]>
* virgl: remove virgl_transfer_queue_listsChia-I Wu2019-07-092-36/+13
| | | | | | | COMPLETED_LIST is always empty. We only need one list. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Alexandros Frantzis <[email protected]>
* virgl: simplify virgl_transfer_queue_extendChia-I Wu2019-07-091-34/+5
| | | | | | | We can reuse virgl_transfer_queue_find_pending. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Alexandros Frantzis <[email protected]>
* virgl: remove transfer after transfer_writeChia-I Wu2019-07-091-2/+1
| | | | | | | | Now that virgl_transfer_queue_is_queued does not search COMPLETED_LIST, we don't need to move transfers to that list. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Alexandros Frantzis <[email protected]>
* virgl: improve virgl_transfer_queue_is_queuedChia-I Wu2019-07-091-30/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Search only the pending list and return immediately on the first hit. When the transfer queue was introduced, the function was used to deal with write transfer -> draw -> write transfer sequence. It was used to tell if the second transfer intersects with the first transfer. If yes, the transfer queue avoided reordering the second transfer to before the draw (by flushing) in case the draw uses the transferred data. With the recent changes to the transfer code, the function is used to deal with write transfer -> readback transfer We want to avoid reordering the readback transfer to before the first transfer (also by flushing). In the old code, we needed to track the compeleted transfers as well to avoid reordering. But in the new code, a readback transfer is guaranteed to see the data from the completed transfers (in other words, it cannot be reoderered to before the already completed transfers). We don't need to search the COMPLETED_LIST. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Alexandros Frantzis <[email protected]>
* virgl: fix transfers_intersect for mipmapsChia-I Wu2019-07-091-7/+2
| | | | | | | | We never use transfers_intersect with textures, but fix it anyway to avoid confusion. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Alexandros Frantzis <[email protected]>
* virgl: fix some false positives in transfers_overlapChia-I Wu2019-07-091-27/+86
| | | | | | | | | Rewrite the function and check z/depth more carefully. We intentionally avoid u_box_test_intersection_2d because it returns true when two boxes touch but do not intersect and can be confusing. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Alexandros Frantzis <[email protected]>
* virgl: Hide internal virgl_resource functionsAlexandros Frantzis2019-07-062-166/+157
| | | | | | | | | | | | Since the transition to virgl_resource_transfer_map(), several previously public virgl_resource functions are not required to be public anymore. We also move the functions earlier in the file so they can be used without functions declarations. Signed-off-by: Alexandros Frantzis <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* virgl: Use virgl_resource_transfer_map for texturesAlexandros Frantzis2019-07-062-60/+4
| | | | | | | | Replace custom texture map code (for maps which don't require resolve) with virgl_resource_transfer_map. Signed-off-by: Alexandros Frantzis <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* virgl: Use virgl_resource_transfer_map for buffersAlexandros Frantzis2019-07-061-79/+1
| | | | | | | Replace custom buffer map code with virgl_resource_transfer_map. Signed-off-by: Alexandros Frantzis <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* virgl: Introduce virgl_resource_transfer_mapAlexandros Frantzis2019-07-062-0/+92
| | | | | | | | | Normal mapping of buffers and textures uses almost identical logic. This commit extracts the this logic in the form of the virgl_resource_transfer_map() helper function. Signed-off-by: Alexandros Frantzis <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* virgl: Clear the valid buffer range when possibleAlexandros Frantzis2019-07-032-0/+24
| | | | | | | | | | | | | | | | | | If we are discarding the whole resource, we don't care about previous contents, and the resource storage is now unused, either because we have created new resource storage, or because we have waited for the existing resource storage to become unused, or because the transfer is unsynchronized. In the last two cases this commit marks the storage as uninitialized, but only if the resource is not host writable (in which case we can't clear the valid range, since that would result in missed readbacks in future transfers). In the first case, when the whole resource discard involves a reallocation, the reallocation and subsequent rebinding already update the valid buffer range appropriately. Signed-off-by: Alexandros Frantzis <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* android: virgl: fix generated virgl_driinfo.h building rulesMauro Rossi2019-06-291-2/+8
| | | | | | | | | | | | | | | | | | | | Changelog in Android makefile: - Add LOCAL_MODULE_CLASS, intermediates and LOCAL_GENERATED_SOURCES - Use LOCAL_EXPORT_C_INCLUDE_DIRS to export $(intermediates) path - Move generated header rules before 'include $(BUILD_STATIC_LIBRARY)' Fixes the following building error: In file included from external/mesa/src/gallium/targets/dri/target.c:1: external/mesa/src/gallium/auxiliary/target-helpers/drm_helper.h:257:16: fatal error: 'virgl/virgl_driinfo.h' file not found #include "virgl/virgl_driinfo.h" ^~~~~~~~~~~~~~~~~~~~~~~ 1 error generated. Fixes: cf800998a ("virgl: Add driinfo file and tie it into the build") Signed-off-by: Mauro Rossi <[email protected]> Review-by: Chih-Wei Huang <[email protected]>
* virgl: Don't allow creating staging pipe_resourcesAlexandros Frantzis2019-06-283-24/+8
| | | | | | | | Staging buffers are now created directly by the virgl_staging_mgr. We don't need to support creating staging pipe_resources. Signed-off-by: Alexandros Frantzis <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* virgl: Use virgl_staging_mgrAlexandros Frantzis2019-06-286-57/+34
| | | | | | | | | | Use an instance of virgl_staging_mgr instead of u_upload_mgr to handle the staging buffer. This removes the need to track the availability of the staging manager, since virgl_staging_mgr can handle concurrent active allocations. Signed-off-by: Alexandros Frantzis <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* virgl: Add tests for virgl_staging_mgrAlexandros Frantzis2019-06-283-0/+424
| | | | | Signed-off-by: Alexandros Frantzis <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* virgl: Introduce virgl_staging_mgrAlexandros Frantzis2019-06-284-0/+230
| | | | | | | | | | | | | | | Add a manager for the staging buffer used in virgl. The staging manager is heavily inspired by u_upload_mgr, but is simpler and is a better fit for virgl's purposes. In particular, the staging manager: * Allows concurrent staging allocations. * Calls the virgl winsys directly to create and map resources, avoiding unnecessarily going through gallium resources and transfers. olv: make virgl_staging_alloc_buffer return a bool Signed-off-by: Alexandros Frantzis <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* virgl: Store the virgl_hw_res for copy transfersAlexandros Frantzis2019-06-286-10/+19
| | | | | | | | | Store the virgl_hw_res instead of the pipe_resource for copy transfer sources. This prepares the codebase for a change to provide only the virgl_hw_res for the staging buffers in upcoming commits. Signed-off-by: Alexandros Frantzis <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* virgl: add VIRGL_DEBUG_XFERChia-I Wu2019-06-253-4/+9
| | | | | | | | When set, do as requested and skip any transfer optimization. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-By: Gert Wollny <[email protected]> Reviewed-By: Alexandros Frantzis <[email protected]>
* virgl: add VIRGL_DEBUG_SYNCChia-I Wu2019-06-253-1/+20
| | | | | | | | When set, wait after every each flush. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-By: Gert Wollny <[email protected]> Reviewed-By: Alexandros Frantzis <[email protected]>
* virgl: fix the value of VIRGL_DEBUG_BGRA_DEST_SWIZZLEChia-I Wu2019-06-252-8/+10
| | | | | | | | | | | | VIRGL_DEBUG_BGRA_DEST_SWIZZLE should use bit 3. Make some cosmetic changes as well. Fixes: a478e56fbd33fa23503b63d41265a1c2f3253ed2 virgl: Add debug flag to bypass driconf to enable the BGRA tweaks Signed-off-by: Chia-I Wu <[email protected]> Reviewed-By: Gert Wollny <[email protected]> Reviewed-By: Alexandros Frantzis <[email protected]>
* android: virgl: fix libmesa_winsys_virgil_common build and dependenciesMauro Rossi2019-06-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes the following building errors and resolves Bug 110922 Fixes gallium_dri target missing symbols at linking. external/mesa/src/gallium/winsys/virgl/drm/Android.mk: error: libmesa_winsys_virgl (STATIC_LIBRARIES android-x86_64) missing libmesa_winsys_virgl_common (STATIC_LIBRARIES android-x86_64) ... external/mesa/src/gallium/winsys/virgl/vtest/Android.mk: error: libmesa_winsys_virgl_vtest (STATIC_LIBRARIES android-x86_64) missing libmesa_winsys_virgl_common (STATIC_LIBRARIES android-x86_64) ... build/core/main.mk:728: error: exiting from previous errors. In file included from external/mesa/src/gallium/winsys/virgl/vtest/virgl_vtest_socket.c:34: external/mesa/src/gallium/winsys/virgl/vtest/virgl_vtest_winsys.h:35:10: fatal error: 'virgl_resource_cache.h' file not found ^~~~~~~~~~~~~~~~~~~~~~~~ 1 error generated. In file included from external/mesa/src/gallium/winsys/virgl/vtest/virgl_vtest_winsys.c:32: external/mesa/src/gallium/winsys/virgl/vtest/virgl_vtest_winsys.h:35:10: fatal error: 'virgl_resource_cache.h' file not found #include "virgl_resource_cache.h" ^~~~~~~~~~~~~~~~~~~~~~~~ 1 error generated. Fixes: b18f09a ("virgl: Introduce virgl_resource_cache") Signed-off-by: Mauro Rossi <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Tested-by: Clayton Craft <[email protected]>
* virgl: Add debug flag to bypass driconf to enable the BGRA tweaksGert Wollny2019-06-202-0/+8
| | | | | | | | This useful for testing, also because with vtest the dri configuration is not read. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: Add a tweak to set the value for emulated queries of GL_SAMPLES_PASSEDGert Wollny2019-06-205-1/+12
| | | | | | | | | | | | | | On GLES hosts GL_SAMPLES_PASSED is emulated by GL_ANY_SAMPLES_PASSED which returns a boolen. With this tweak the value that is returned if any sample passed can be set. This may be of iterest when an application decides whether some geometry is rendered based on an amount of visibility and not just a binary desicion. virgelrenderer sets a default of 1024 on th host. v2: Remove reference from virgl and correct description (Emil) v3: Send the tweak binary encoded instead of using strings (Gurchetan) Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: Add tweak to apply a swizzle when drawing/blitting to a emulated BGRA ↵Gert Wollny2019-06-205-0/+9
| | | | | | | | | | | | texture With Qemu this final swizzle is not needed, but with vtest it is, i.e. it depends on how a program using virglrenderer uses the surface that is rendered to, hence a tweak is added. v2: Update description and fix spelling (Emil) v3: Send tweak as binary value instead of using strings (Gurchetan) Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: Add driconf tweak for emulating BGRA surfaces on GLESGert Wollny2019-06-203-0/+10
| | | | | | | | | | | These tweaks are used to fix rendering issues with Valve games and at least also "The Raven Remastered" when run on a GLES host. v2: Fix type in define and remove virgl from driconf option (Emil) v3: Encode tweak binary instead of using strings (Gurchetan) Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: Add override for BGRA format to use swizzled SRGB formatGert Wollny2019-06-204-1/+27
| | | | | | | | | | | Tie in the check whether the host supports tweaks and whether this tweak is enabled. v2: Add comment about the emulated formats not being used directly in the guest (Gurchetan) Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: Add code to accept BGRx_SRGB as RGBx_SRGBGert Wollny2019-06-202-3/+23
| | | | | | | This will be enabled in later patches by the emulation tweak. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: Add skeleton to evaluate cap and send tweaksGert Wollny2019-06-205-0/+31
| | | | | Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: factor out format host bits checkGert Wollny2019-06-201-16/+17
| | | | | | | This will make it a single location when we want to replace a format. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* gallium/virgl: Add code path for virgl to read driconfGert Wollny2019-06-202-2/+3
| | | | | | | | | | | | This works only for the drm variant of virgl and not for the vtest variant. v2: Rebase, replace the configuration query function by a pointer to the configuration data. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Emil Velikov <[email protected]> (v1) Reviewed-by: Gurchetan Singh <[email protected]>
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