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* virgl: Clear the valid buffer range when possibleAlexandros Frantzis2019-07-032-0/+24
* android: virgl: fix generated virgl_driinfo.h building rulesMauro Rossi2019-06-291-2/+8
* virgl: Don't allow creating staging pipe_resourcesAlexandros Frantzis2019-06-283-24/+8
* virgl: Use virgl_staging_mgrAlexandros Frantzis2019-06-286-57/+34
* virgl: Add tests for virgl_staging_mgrAlexandros Frantzis2019-06-283-0/+424
* virgl: Introduce virgl_staging_mgrAlexandros Frantzis2019-06-284-0/+230
* virgl: Store the virgl_hw_res for copy transfersAlexandros Frantzis2019-06-286-10/+19
* virgl: add VIRGL_DEBUG_XFERChia-I Wu2019-06-253-4/+9
* virgl: add VIRGL_DEBUG_SYNCChia-I Wu2019-06-253-1/+20
* virgl: fix the value of VIRGL_DEBUG_BGRA_DEST_SWIZZLEChia-I Wu2019-06-252-8/+10
* android: virgl: fix libmesa_winsys_virgil_common build and dependenciesMauro Rossi2019-06-211-1/+1
* virgl: Add debug flag to bypass driconf to enable the BGRA tweaksGert Wollny2019-06-202-0/+8
* virgl: Add a tweak to set the value for emulated queries of GL_SAMPLES_PASSEDGert Wollny2019-06-205-1/+12
* virgl: Add tweak to apply a swizzle when drawing/blitting to a emulated BGRA ...Gert Wollny2019-06-205-0/+9
* virgl: Add driconf tweak for emulating BGRA surfaces on GLESGert Wollny2019-06-203-0/+10
* virgl: Add override for BGRA format to use swizzled SRGB formatGert Wollny2019-06-204-1/+27
* virgl: Add code to accept BGRx_SRGB as RGBx_SRGBGert Wollny2019-06-202-3/+23
* virgl: Add skeleton to evaluate cap and send tweaksGert Wollny2019-06-205-0/+31
* virgl: factor out format host bits checkGert Wollny2019-06-201-16/+17
* gallium/virgl: Add code path for virgl to read driconfGert Wollny2019-06-202-2/+3
* virgl: Add driinfo file and tie it into the buildGert Wollny2019-06-203-2/+36
* virgl: Support VIRGL_BIND_SHAREDDavid Riley2019-06-192-0/+3
* virgl: fix sync issue regarding discard/unsync transfersChia-I Wu2019-06-181-5/+15
* virgl_hw: add YUV supportGurchetan Singh2019-06-181-0/+6
* virgl: sync to virglrenderer virgl_hw.hGurchetan Singh2019-06-181-3/+10
* virgl: Assume sRGB write control for older guest kernels or virglrenderer hostsGert Wollny2019-06-171-1/+2
* virgl: better support for PIPE_TRANSFER_DISCARD_WHOLE_RESOURCEChia-I Wu2019-06-174-25/+92
* virgl: add virgl_rebind_resourceChia-I Wu2019-06-174-0/+148
* virgl: save virgl_hw_res in virgl_transferChia-I Wu2019-06-175-14/+22
* virgl: add resource_reference to virgl_winsysChia-I Wu2019-06-172-2/+4
* virgl: virgl_transfer should own its virgl_resourceChia-I Wu2019-06-122-8/+6
* virgl: pass virgl_context to transfer create/destroyChia-I Wu2019-06-125-22/+21
* virgl: init transfer queue from virgl_contextChia-I Wu2019-06-123-10/+11
* virgl: clean up virgl_transfer_queue.hChia-I Wu2019-06-122-1/+13
* virgl: Work around possible memory exhaustionAlexandros Frantzis2019-06-073-3/+22
* virgl: Remove incorrect resource wait conditionAlexandros Frantzis2019-06-071-13/+0
* virgl: Use copy transfers for texturesAlexandros Frantzis2019-06-072-9/+87
* virgl: Use buffer copy transfers to avoid waiting when mappingAlexandros Frantzis2019-06-076-6/+137
* virgl: Support copy transfersAlexandros Frantzis2019-06-075-5/+70
* virgl: Add copy_transfer3d definitionsAlexandros Frantzis2019-06-072-0/+9
* virgl: Support VIRGL_BIND_STAGINGAlexandros Frantzis2019-06-073-4/+16
* virgl: Avoid unfinished transfer_get with PIPE_TRANSFER_DONTBLOCKAlexandros Frantzis2019-06-071-9/+12
* virgl: More info about chosen alignment valueAlexandros Frantzis2019-06-071-0/+5
* virgl: store all info about atomic buffersChia-I Wu2019-06-072-16/+23
* virgl: add shader images to virgl_shader_binding_stateChia-I Wu2019-06-072-14/+27
* virgl: add SSBOs to virgl_shader_binding_stateChia-I Wu2019-06-072-14/+26
* virgl: add UBOs to virgl_shader_binding_stateChia-I Wu2019-06-072-20/+37
* virgl: add virgl_shader_binding_stateChia-I Wu2019-06-072-43/+44
* virgl: Enable CAP_CLIP_HALFZ if host supports itGert Wollny2019-06-062-1/+3
* virgl: resolve to correct level during texture readChia-I Wu2019-06-041-2/+2
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 03:22:44 +0000