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path: root/src/gallium/drivers/virgl
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* virgl_hw: add YUV supportGurchetan Singh2019-06-181-0/+6
* virgl: sync to virglrenderer virgl_hw.hGurchetan Singh2019-06-181-3/+10
* virgl: Assume sRGB write control for older guest kernels or virglrenderer hostsGert Wollny2019-06-171-1/+2
* virgl: better support for PIPE_TRANSFER_DISCARD_WHOLE_RESOURCEChia-I Wu2019-06-174-25/+92
* virgl: add virgl_rebind_resourceChia-I Wu2019-06-174-0/+148
* virgl: save virgl_hw_res in virgl_transferChia-I Wu2019-06-175-14/+22
* virgl: add resource_reference to virgl_winsysChia-I Wu2019-06-172-2/+4
* virgl: virgl_transfer should own its virgl_resourceChia-I Wu2019-06-122-8/+6
* virgl: pass virgl_context to transfer create/destroyChia-I Wu2019-06-125-22/+21
* virgl: init transfer queue from virgl_contextChia-I Wu2019-06-123-10/+11
* virgl: clean up virgl_transfer_queue.hChia-I Wu2019-06-122-1/+13
* virgl: Work around possible memory exhaustionAlexandros Frantzis2019-06-073-3/+22
* virgl: Remove incorrect resource wait conditionAlexandros Frantzis2019-06-071-13/+0
* virgl: Use copy transfers for texturesAlexandros Frantzis2019-06-072-9/+87
* virgl: Use buffer copy transfers to avoid waiting when mappingAlexandros Frantzis2019-06-076-6/+137
* virgl: Support copy transfersAlexandros Frantzis2019-06-075-5/+70
* virgl: Add copy_transfer3d definitionsAlexandros Frantzis2019-06-072-0/+9
* virgl: Support VIRGL_BIND_STAGINGAlexandros Frantzis2019-06-073-4/+16
* virgl: Avoid unfinished transfer_get with PIPE_TRANSFER_DONTBLOCKAlexandros Frantzis2019-06-071-9/+12
* virgl: More info about chosen alignment valueAlexandros Frantzis2019-06-071-0/+5
* virgl: store all info about atomic buffersChia-I Wu2019-06-072-16/+23
* virgl: add shader images to virgl_shader_binding_stateChia-I Wu2019-06-072-14/+27
* virgl: add SSBOs to virgl_shader_binding_stateChia-I Wu2019-06-072-14/+26
* virgl: add UBOs to virgl_shader_binding_stateChia-I Wu2019-06-072-20/+37
* virgl: add virgl_shader_binding_stateChia-I Wu2019-06-072-43/+44
* virgl: Enable CAP_CLIP_HALFZ if host supports itGert Wollny2019-06-062-1/+3
* virgl: resolve to correct level during texture readChia-I Wu2019-06-041-2/+2
* virgl: fix texture resolving with compressed formatsChia-I Wu2019-06-041-12/+17
* virgl: fix readback with pending transfersChia-I Wu2019-05-291-6/+26
* virgl: remove an incorrect check in virgl_res_needs_flushChia-I Wu2019-05-241-15/+0
* virgl: reemit resources on first draw/clear/computeChia-I Wu2019-05-241-6/+24
* virgl: add missing emit_res for SO targetsChia-I Wu2019-05-241-2/+8
* gallium: Change PIPE_CAP_TGSI_FS_FBFETCH bool to PIPE_CAP_FBFETCH countKenneth Graunke2019-05-231-2/+3
* virgl: track valid buffer range for transfer syncChia-I Wu2019-05-227-20/+59
* virgl: remove support for buffer surfacesChia-I Wu2019-05-222-19/+15
* virgl: handle NULL shader resource explicitlyChia-I Wu2019-05-221-3/+3
* virgl: handle DONT_BLOCK and MAP_DIRECTLYChia-I Wu2019-05-154-7/+45
* virgl: add virgl_resource_transfer_prepareChia-I Wu2019-05-154-55/+49
* virgl: honor DISCARD_WHOLE_RESOURCE in virgl_res_needs_readbackChia-I Wu2019-05-151-1/+2
* virgl: clean up virgl_res_needs_readbackChia-I Wu2019-05-151-5/+16
* virgl: clean up virgl_res_needs_flushChia-I Wu2019-05-141-2/+34
* virgl: comment on a sync issue in transfersChia-I Wu2019-05-142-0/+20
* virgl: PIPE_TRANSFER_READ does not imply flushChia-I Wu2019-05-141-4/+1
* virgl: do not skip readback because of explicit flushChia-I Wu2019-05-141-3/+0
* virgl: remove unused virgl_transfer_inline_writeChia-I Wu2019-05-142-42/+0
* gallium: Redefine the max texture 2d cap from _LEVELS to _SIZE.Eric Anholt2019-05-131-3/+3
* virgl: do not use inline writes for subdataChia-I Wu2019-05-061-4/+7
* virgl: rework queriesChia-I Wu2019-05-061-45/+71
* virgl: export resource_is_busy from winsysChia-I Wu2019-05-061-0/+2
* virgl: Re-use and extend queue transfers for intersecting buffer subdatas.David Riley2019-05-011-0/+46
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