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path: root/src/gallium/drivers/virgl/virgl_resource.c
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* gallium: switch boolean -> bool at the interface definitionsIlia Mirkin2019-07-221-4/+4
* virgl: fix a sync issue in virgl_buffer_transfer_extendChia-I Wu2019-07-191-62/+15
* virgl: rework virgl_transfer_queue_extendChia-I Wu2019-07-191-4/+2
* virgl: fix virgl_buffer_transfer_extendChia-I Wu2019-07-191-0/+1
* virgl: Set meta data for textures from handle.Lepton Wu2019-07-171-0/+1
* gallium: use MAP_DIRECTLY to mean supression of DISCARD in buffer_subdataMarek Olšák2019-07-151-4/+6
* virgl: Hide internal virgl_resource functionsAlexandros Frantzis2019-07-061-142/+157
* virgl: Use virgl_resource_transfer_map for texturesAlexandros Frantzis2019-07-061-0/+1
* virgl: Introduce virgl_resource_transfer_mapAlexandros Frantzis2019-07-061-0/+84
* virgl: Clear the valid buffer range when possibleAlexandros Frantzis2019-07-031-0/+3
* virgl: Use virgl_staging_mgrAlexandros Frantzis2019-06-281-24/+14
* virgl: Store the virgl_hw_res for copy transfersAlexandros Frantzis2019-06-281-3/+11
* virgl: add VIRGL_DEBUG_XFERChia-I Wu2019-06-251-4/+7
* virgl: Add override for BGRA format to use swizzled SRGB formatGert Wollny2019-06-201-0/+10
* virgl: fix sync issue regarding discard/unsync transfersChia-I Wu2019-06-181-5/+15
* virgl: better support for PIPE_TRANSFER_DISCARD_WHOLE_RESOURCEChia-I Wu2019-06-171-25/+70
* virgl: save virgl_hw_res in virgl_transferChia-I Wu2019-06-171-0/+7
* virgl: add resource_reference to virgl_winsysChia-I Wu2019-06-171-1/+1
* virgl: virgl_transfer should own its virgl_resourceChia-I Wu2019-06-121-1/+5
* virgl: pass virgl_context to transfer create/destroyChia-I Wu2019-06-121-4/+4
* virgl: Work around possible memory exhaustionAlexandros Frantzis2019-06-071-3/+14
* virgl: Remove incorrect resource wait conditionAlexandros Frantzis2019-06-071-13/+0
* virgl: Use copy transfers for texturesAlexandros Frantzis2019-06-071-4/+52
* virgl: Use buffer copy transfers to avoid waiting when mappingAlexandros Frantzis2019-06-071-2/+82
* virgl: Support copy transfersAlexandros Frantzis2019-06-071-0/+3
* virgl: Support VIRGL_BIND_STAGINGAlexandros Frantzis2019-06-071-1/+1
* virgl: Avoid unfinished transfer_get with PIPE_TRANSFER_DONTBLOCKAlexandros Frantzis2019-06-071-9/+12
* virgl: fix readback with pending transfersChia-I Wu2019-05-291-6/+26
* virgl: remove an incorrect check in virgl_res_needs_flushChia-I Wu2019-05-241-15/+0
* virgl: track valid buffer range for transfer syncChia-I Wu2019-05-221-19/+31
* virgl: handle DONT_BLOCK and MAP_DIRECTLYChia-I Wu2019-05-151-2/+17
* virgl: add virgl_resource_transfer_prepareChia-I Wu2019-05-151-5/+44
* virgl: honor DISCARD_WHOLE_RESOURCE in virgl_res_needs_readbackChia-I Wu2019-05-151-1/+2
* virgl: clean up virgl_res_needs_readbackChia-I Wu2019-05-151-5/+16
* virgl: clean up virgl_res_needs_flushChia-I Wu2019-05-141-2/+34
* virgl: do not skip readback because of explicit flushChia-I Wu2019-05-141-3/+0
* virgl: do not use inline writes for subdataChia-I Wu2019-05-061-4/+7
* virgl: Re-use and extend queue transfers for intersecting buffer subdatas.David Riley2019-05-011-0/+46
* virgl: add support for missing command buffer binding.Dave Airlie2019-04-091-1/+1
* virgl: use uint16_t mask instead of separate booleansGurchetan Singh2019-03-131-8/+7
* virgl: use virgl_transfer_inline_write even lessGurchetan Singh2019-02-151-1/+1
* virgl: use transfer queueGurchetan Singh2019-02-151-0/+2
* virgl: add extra checks in virgl_res_needs_flush_waitGurchetan Singh2019-02-151-4/+9
* virgl: pass virgl transfer to virgl_res_needs_flush_waitGurchetan Singh2019-02-151-3/+4
* virgl: when creating / freeing transfers, pass slab pool directlyGurchetan Singh2019-02-151-5/+4
* virgl: track level cleanliness rather than resource cleanlinessGurchetan Singh2019-02-151-4/+8
* virgl: use virgl_resource_dirty helperGurchetan Singh2019-02-151-0/+6
* virgl: add ability to do finer grain dirty trackingGurchetan Singh2019-02-151-2/+4
* virgl: move resource creation / import / destruction to common codeGurchetan Singh2018-12-191-10/+74
* virgl: make transfer code with PIPE_BUFFER targetsGurchetan Singh2018-12-191-2/+4
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