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* broadcom/vc5: Fix regression in the page-cache slice size alignment.Eric Anholt2018-02-281-3/+6
| | | | | | | We need to align the size of the slice, not the offset of the next slice. Fixes KHR-GLES3.texture_repeat_mode.rgba32ui_11x131_2_clamp_to_edge. Fixes: b4b4ada7616d ("broadcom/vc5: Fix layout of 3D textures.")
* broadcom/vc5: Fix layout of 3D textures.Eric Anholt2018-02-232-32/+81
| | | | | | Cube maps are entire miptrees repeated, while 3D textures have each level have all of its layers next to each other. Fixes tex3d and tex-miplevel-selection GL2:texture() 3D.
* broadcom/vc5: Ignore unused usage flags in is_format_supported.Eric Anholt2018-02-231-27/+16
| | | | | | | | Like for vc4, the new DISPLAY_TARGET flag ended up causing no formats to match. Just drop the whole retval == usage thing and return early when we hit a known unsupported case. Fixes: f7604d8af521 ("st/dri: only expose config formats that are display targets")
* gallium: allow drivers to impose BO flags restrictions on constant buffer 0Marek Olšák2018-02-171-0/+1
| | | | Required by radeonsi for optimal behavior.
* gallium: drop all the guard band float caps.Dave Airlie2018-02-141-5/+0
| | | | | | | | | | Nobody queries these and nobody sets them to anything useful, the docs say TODO. Drop them until a use appears. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* broadcom/vc5: Ignore samplers for finding uniform offsets.Eric Anholt2018-02-051-1/+12
| | | | | | | | Fixes: KHR-GLES3.shaders.struct.uniform.sampler_array_fragment KHR-GLES3.shaders.struct.uniform.sampler_array_vertex KHR-GLES3.shaders.struct.uniform.sampler_nested_fragment KHR-GLES3.shaders.struct.uniform.sampler_nested_vertex
* broadcom/vc5: Fix non-mipfiltered sampling.Eric Anholt2018-02-051-1/+6
| | | | | We need to clamp the LOD to 0 if mip filtering is disabled. This is part of fixing KHR-GLES3.shaders.struct.uniform.sampler_array_fragment.
* broadcom/vc5: Enable UIF XOR on textures.Eric Anholt2018-02-023-7/+40
| | | | | | | | | | This should increase performance by reducing SDRAM bank conflicts when crossing between UIF columns (particularly on power-of-two height textures). The uif_xor_disable setup is dropped, since we need to allow XOR on lower miplevels even when level 0 is XOR. The level 0 force UIF and level 0 XOR flags should handle setting XOR properly on imported buffers.
* broadcom/vc5: Fix alignment of miplevel 1 with UIF.Eric Anholt2018-02-023-15/+31
| | | | | | | The alignment here means that we can't get back the padded height from the size/stride any more, so it's now a field in the slice as well. Fixes piglit fbo-generatemipmap-formats RGBA16 NPOT.
* broadcom/vc5: Switch our RGBA4 support to the new gallium format.Eric Anholt2018-02-021-2/+1
| | | | | Fixes fbo-generatemipmap-formats, fbo-alphatest-formats, etc. tests for GL_RGBA4, GL_RGB4, GL_RGBA2, etc.
* broadcom/vc5: Fix image_h setup for both loads and stores.Eric Anholt2018-02-011-3/+2
| | | | | | | The image_h for the tiling algorithm needs to be the padded-to-a-uifblock height of the level, not the unpadded height or the height of level 0. Fixes some cases of KHR-GLES3.texture_repeat_mode.* and depthstencil-render-miplevels.
* broadcom/vc5: Add appropriate height padding for bank conflicts.Eric Anholt2018-02-014-0/+63
| | | | | | | I thought I didn't need this because I was doing level-0-always-UIF and that the pad there would propagate down, but it turns out that for level 1 the padding ends up being chosen by the HW. This brings us closer to being able to turn on UIF XOR for increased performance, as well.
* broadcom/vc5: Simplify separate stencil surface setup.Eric Anholt2018-02-013-99/+77
| | | | | | | | | If we just make another gallium surface for the separate stencil, it's a lot easier to keep track of which set of fields we're using in RCL setup. This also incidentally fixes a little bug in setting up the surface's padded height for separate stencil when the UIF-ness changes at different levels of Z versus stencil.
* broadcom/vc5: Rename the UIFCFG register in the UAPI.Eric Anholt2018-02-012-2/+2
| | | | | | This matches the naming of the other hub regs we get, and I don't know for sure if UIFCFG will be the same register between the hub and the cores on all versions.
* broadcom/vc5: Skip over missing color buffers for a couple of checks.Eric Anholt2018-02-012-0/+6
| | | | Fixes crashes in piglit alpha-to-coverage-no-draw-buffer-zero 2
* broadcom/vc5: Add the missing PIPE_CAP_FENCE_SIGNAL.Eric Anholt2018-02-011-0/+1
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* broadcom/vc5: Don't forget to get the BO offset when opening a dmabuf.Eric Anholt2018-01-271-0/+12
| | | | Fixes black display in DRI due to storing to 0x00000000.
* broadcom/vc5: Enable the driver on V3D 4.2.Eric Anholt2018-01-271-1/+6
| | | | | | The changes in 4.2 haven't impacted any of our CL or state struct entries that I can see, so I haven't enabled custom compile for doing 4.2 instead of 4.1.
* automake: vc5: remove non-applicable v3dx_simulator.hEmil Velikov2018-01-251-1/+0
| | | | Signed-off-by: Emil Velikov <[email protected]>
* broadcom/vc5: Fix source file name.Vinson Lee2018-01-211-1/+1
| | | | | | Fixes: c9b2cb78972d ("vc5: add missing files to the tarball") Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* broadcom/vc5: Add missing include paths.Vinson Lee2018-01-211-2/+2
| | | | | | Fixes: 954a704da305 ("broadcom/vc5: Port the RCL setup to V3D4.1.") Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* autotools: include meson build files in tarballDylan Baker2018-01-191-0/+2
| | | | | | | | | | | | This adds the meson.build, meson_options.txt, and a few scripts that are used exclusively by the meson build. v2: - Remove accidentally included changes needed to test make dist with LLVM > 3.9 Signed-off-by: Dylan Baker <[email protected]> Acked-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* vc5: add missing files to the tarballEmil Velikov2018-01-181-0/+5
| | | | Signed-off-by: Emil Velikov <[email protected]>
* gallium: remove PIPE_CAP_USER_CONSTANT_BUFFERSMarek Olšák2018-01-171-1/+0
| | | | | Reviewed-by: Roland Scheidegger <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium: remove PIPE_CAP_TEXTURE_SHADOW_MAPMarek Olšák2018-01-171-1/+0
| | | | | Reviewed-by: Roland Scheidegger <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium: remove PIPE_CAP_TWO_SIDED_STENCILMarek Olšák2018-01-171-1/+0
| | | | | Reviewed-by: Roland Scheidegger <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* broadcom/vc5: Fix up channel swizzling for textures on 4.x.Eric Anholt2018-01-121-2/+5
| | | | | | | | I had 3.x putting swizzling in the texture state only for 16-bit texture returns, and in the shader for 32-bit. This may be due to having mixed up the return channel setup on 3.x back before I had moved it into the compiler. On 4.x, the non-border-color texwrap tests are passing nicely with both 16 and 32-bit returns with swizzling in the texture state.
* broadcom/vc5: Port the draw-time state emission to V3D 4.1.Eric Anholt2018-01-127-27/+76
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* broadcom/vc5: Rename V3D 3.x Flat Shade Action to match v4.x naming.Eric Anholt2018-01-121-5/+5
| | | | | Now that the actions are reused for centroid and nonperspective, give them a more generic name.
* broadcom/vc5: Update pixel center setup for V3D 4.x.Eric Anholt2018-01-121-2/+12
| | | | | The fxcd/fycd instructions now return half-integer pixel centers when not doing sample-rate shading.
* broadcom/vc5: Print the buffer name in simulator overflow checks.Eric Anholt2018-01-121-2/+4
| | | | Revealed that I was writing past the TSDA, not the Z buffer as I expected.
* broadcom/vc5: Update state setup for V3D 4.1.Eric Anholt2018-01-127-14/+206
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* broadcom/vc5: Set up depth formats for V3D 4.x.Eric Anholt2018-01-121-1/+12
| | | | | We no longer have the small depth-specific output format enum, and instead depth is just at the end of the output image format enum.
* broadcom/vc5: Always use the RGBA8 formats for RGBX8.Eric Anholt2018-01-121-3/+7
| | | | | The RGBX8 formats were dropped from V3D 4.x, but we don't really need them anyway (we already handle other non-alpha formats by forcing A to 1).
* broadcom/vc5: Move the formats table to per-V3D-version compile.Eric Anholt2018-01-1212-337/+451
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* broadcom/vc5: Use THRSW to enable multi-threaded shaders.Eric Anholt2018-01-121-3/+26
| | | | | This is a major performance boost on all of V3D, but is required on V3D 4.x where shaders are always either 2- or 4-threaded.
* broadcom/vc5: Port drawing commands to V3D 4.x.Eric Anholt2018-01-129-20/+93
| | | | | This required extending the CL submit ioctl, because the tile alloc/state buffer setup has moved from the BCL to register writes.
* broadcom/vc5: Enable the driver on V3D 4.1Eric Anholt2018-01-121-1/+1
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* broadcom/vc5: Port the simulator to support V3D 4.1Eric Anholt2018-01-129-125/+216
| | | | | | | This required moving the register accesses to a separate v3dx file, since the register definitions for each V3D version collide. It seems that initializing the v3d_hw from a file dictating 3.3 (v3d_simulator_wrapper.cpp) is safe, though.
* broadcom/vc5: Port the RCL setup to V3D4.1.Eric Anholt2018-01-127-58/+360
| | | | | | | The TLB load/store path is rebuilt in this version. There is no longer a single-byte resolved store or the 3-byte extended store. Instead, you get to always use general loads/stores (which, honestly, was tempting even in previous versions).
* broadcom/vc5: Fix per-tile extra clear packet.Eric Anholt2018-01-121-1/+1
| | | | | I accidentally emitted this into the RCL instead of the per-tile generic list, so we wouldn't get tiles after the first cleared.
* broadcom/vc5: Move the TLB loads and stores to helper functions.Eric Anholt2018-01-121-35/+50
| | | | | This is going to get more complicated with V3D 4.1 support, which redoes all the TLB packets.
* broadcom/vc5: Convert vc5_cl.h to use the V3DX() macros.Eric Anholt2018-01-127-10/+24
| | | | | | To conditionally compile cl_emit() macros per V3D version, we need it to expand to whatever V3D we're building for. This required emitting #define V3D_VERSION 33 in all our currently 3.3-only code.
* meson: Use dependencies for nirDylan Baker2018-01-111-3/+4
| | | | | | | | | | | | | | | | | This creates two new internal dependencies, idep_nir_headers and idep_nir. The former encapsulates the generation of nir_opcodes.h and nir_builder_opcodes.h and adding src/compiler/nir as an include path. This ensures that any target that needs nir headers will have the includes and that the generated headers will be generated before the target is build. The second, idep_nir, includes the first and additionally links to libnir. This is intended to make it easier to avoid race conditions in the build when using nir, since the number of consumers for libnir and it's headers are quite high. Acked-by: Eric Engestrom <[email protected]> Signed-off-by: Dylan Baker <[email protected]>
* braodcom/vc5: Fix internal type/bpp for RGB10_A2UI images.Eric Anholt2018-01-031-0/+1
| | | | | I found that we were getting GPU hangs on most tests rendering to them, and the simulator was assertion failing.
* broadcom/vc5: Try to fix up compressed texture load/store.Eric Anholt2018-01-031-2/+15
| | | | | | We were trying to load/store the logical width/height number of compressed blocks. As long as the textures were large, single-level, and the load/store at (0,0), it kind of worked.
* broadcom/vc5: Fix image_h value for CPU-side tiling on miplevels > 1.Eric Anholt2018-01-031-1/+2
| | | | | Fixes overflow that caused failure in dEQP-GLES3.functional.texture.filtering.2d.sizes.128x128_linear.
* broadcom/vc5: Disable early Z when the stencil func isn't ALWAYS.Eric Anholt2018-01-031-1/+3
| | | | | | | | Apparently the other funcs will have observable differences when early Z is enabled. Fixes (new) simulator assertion failures in dEQP-GLES3.functional.rasterizer_discard.basic.clear_depth.
* broadcom/vc5: Introduce enums for internal depth/type, with V3D prefixes.Eric Anholt2018-01-035-57/+57
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* broadcom/vc5: Turn the output image format into an enum.Eric Anholt2018-01-031-45/+45
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