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* vc4: Add support for GL 1.0 logic ops.Eric Anholt2014-12-081-2/+60
* vc4: Add support for TGSI_OPCODE_UCMP.Eric Anholt2014-12-081-0/+12
* vc4: Try swapping the regfile A to B to pair instructions.Eric Anholt2014-12-051-2/+62
* vc4: Allow pairing of some instructions that disagree about the WS bit.Eric Anholt2014-12-051-1/+47
* vc4: Add separate write-after-read dependency tracking for pairing.Eric Anholt2014-12-051-20/+58
* vc4: Fix inverted priority of instructions for QPU scheduling.Eric Anholt2014-12-051-10/+10
* vc4: Refuse to merge two ops that both access shared functions.Eric Anholt2014-12-053-36/+55
* vc4: Allow dead code elimination of color reads.Eric Anholt2014-12-051-1/+1
* vc4: Add a debug flag for waiting for sync on submit.Eric Anholt2014-12-053-0/+11
* vc4: Pair up QPU instructions when scheduling.Eric Anholt2014-12-013-38/+105
* vc4: Introduce scheduling of QPU instructions.Eric Anholt2014-12-016-126/+722
* vc4: Drop the explicit scoreboard wait.Eric Anholt2014-12-011-12/+11
* vc4: Also deal with VPM reads at thread end.Eric Anholt2014-12-011-2/+6
* vc4: Fix assertion about SFU versus texturing.Eric Anholt2014-12-011-3/+4
* vc4: Add another check for invalid TLB scoreboard handling.Eric Anholt2014-12-013-8/+39
* vc4: Fix some inconsistent indentation.Eric Anholt2014-11-241-6/+6
* vc4: Don't forget to actually connect the fence code.Eric Anholt2014-11-241-0/+2
* vc4: Add a note about a piece of errata I've learned about.Eric Anholt2014-11-241-0/+4
* vc4: Update for new kernel ABI with async execution and waits.Eric Anholt2014-11-209-3/+250
* vc4: Emit semaphore instructions for new kernel ABI.Eric Anholt2014-11-183-6/+87
* vc4: Mark a big array as const.Eric Anholt2014-11-181-1/+1
* vc4: Avoid reusing a pointer from c->outputs[] after add_output().Eric Anholt2014-11-121-5/+6
* vc4: Fix assumption of TGSI OUT[0] being POSITION in the VS.Eric Anholt2014-11-121-5/+5
* vc4: Add support for ARL and indirect register access on TGSI_FILE_CONSTANT.Eric Anholt2014-10-2810-34/+407
* vc4: Fix mixup of return type in reloc_tex().Eric Anholt2014-10-281-2/+2
* vc4: Drop redundant check for is_tmu_write().Eric Anholt2014-10-281-3/+0
* vc4: Don't forget to validate code that's got PROG_END on it.Eric Anholt2014-10-281-5/+6
* vc4: Add .dir-locals.el for kernel style in the kernel code.Eric Anholt2014-10-281-0/+12
* vc4: Fix a couple missing '\n's in error output.Eric Anholt2014-10-282-2/+2
* gallium: introduce PIPE_CAP_CLIP_HALFZ.Mathias Fröhlich2014-10-241-0/+1
* vc4: Reuse uniform_data/contents indices when making uniforms.Eric Anholt2014-10-241-0/+7
* vc4: When asked to discard-map a whole resource, discard it.Eric Anholt2014-10-241-14/+28
* vc4: Refactor flushing before mapping a BO.Eric Anholt2014-10-243-12/+13
* vc4: Allow dead code elimination of unused varyings.Eric Anholt2014-10-245-5/+31
* vc4: Add debug output to match shaderdb info to program dumps.Eric Anholt2014-10-244-7/+29
* gallium: add PIPE_SHADER_CAP_MAX_OUTPUTS and use it in st/mesaMarek Olšák2014-10-211-0/+2
* vc4: Fix SRC_ALPHA_SATURATE blending.Eric Anholt2014-10-211-3/+11
* vc4: Fix stencil writemask handling.Eric Anholt2014-10-211-2/+2
* vc4: Don't look at back stencil state unless two-sided stencil is enabled.Eric Anholt2014-10-211-2/+6
* vc4: Translate 4-byte index buffers to 2 bytes.Eric Anholt2014-10-194-10/+92
* vc4: Add support for rebasing texture levels so firstlevel == 0.Eric Anholt2014-10-195-3/+83
* vc4: Apply a Newton-Raphson step to improve RSQEric Anholt2014-10-181-2/+20
* vc4: Apply a Newton-Raphson step to improve RCP.Eric Anholt2014-10-181-1/+17
* vc4: Add a little bit more packet parsing to make dump reading easier.Eric Anholt2014-10-181-19/+114
* vc4: Make some assertions about how many flushes/EOFs the simulator sees.Eric Anholt2014-10-174-9/+26
* vc4: Fix accidental dropping of the low bits of the store tilebuffer packet.Eric Anholt2014-10-171-3/+5
* vc4: Set the primitive list format at the start of rendering.Eric Anholt2014-10-172-0/+15
* vc4: Replace the FLUSH_ALL with FLUSH.Eric Anholt2014-10-171-1/+3
* vc4: Add some comments about state management.Eric Anholt2014-10-172-0/+11
* vc4: Make sure there's exactly 1 tile store per tile coords packet.Eric Anholt2014-10-171-15/+64
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