| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Rhys Perry <[email protected]>
Reviewed-by: Brian Paul <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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util_is_power_of_two_or_zero
The new name make the zero-input behavior more obvious. The next
patch adds a new function with different zero-input behavior.
Signed-off-by: Ian Romanick <[email protected]>
Suggested-by: Matt Turner <[email protected]>
Reviewed-by: Alejandro Piñeiro <[email protected]>
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As the other VC4 files do. Otherwise, it won't find nir_builder.h
v2: add path in source code rather changing autotools (Emil)
Reviewed-by: Emil Velikov <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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It would be nice to support perfmon with simulator, and might be a useful
tool for regression testing performance (since the simulator would be
deterministic).
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Drawing a 1080p YV12 video stream generated by MMAL goes from 10.5 FPS to
36.
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We're going to use UBO loads for implementing YUV linear-to-T-format
blits.
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The imported drm_fourcc.h handles it now.
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The V3D engine provides several perf counters.
Implement ->get_driver_query_[group_]info() so that these counters are
exposed through the GL_AMD_performance_monitor extension.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Eric Anholt <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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This got us into trouble recently, so just remove it entirely.
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Previously we would assertion fail about having no hardware format. This
is enough to get kmscube -M nv12-2img working.
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When we set up the shadow resource we were copying the original resource
as the template, including its prsc->next field. When we shadowed the
first YUV plane's resource for linear-to-tiled conversion, we would end up
unbalancing the refcount on the shadow resource's destruction.
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Trying to track down the YUV EGLImage use-after-free, it helps to see what
the mystery objects are that are being refcounted.
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It would be broken if NULL was passed to it anyway, since it wouldn't
participate in screen->bo_handles management.
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Improves u_debug_refcount output.
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This is part of supporting YUV textures -- MMAL will be handing us a
single GEM BO with the planes at offsets within it, and MMAL-decided
stride.
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We were failing the retval == usage check at the end.
Fixes: f7604d8af521 ("st/dri: only expose config formats that are display targets")
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Required by radeonsi for optimal behavior.
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Nobody queries these and nobody sets them to anything useful,
the docs say TODO.
Drop them until a use appears.
Reviewed-by: Roland Scheidegger <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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This will be used for freedreno and vc4 which require all inputs
and outputs to be copied to temps.
Reviewed-by: Marek Olšák <[email protected]>
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Protects semaphore signaling functionality required by GL_EXT_semaphore.
v2: s/semaphore/fence
Signed-off-by: Andres Rodriguez <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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This adds the meson.build, meson_options.txt, and a few scripts that are
used exclusively by the meson build.
v2: - Remove accidentally included changes needed to test make dist with
LLVM > 3.9
Signed-off-by: Dylan Baker <[email protected]>
Acked-by: Eric Engestrom <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
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Reviewed-by: Roland Scheidegger <[email protected]>
Tested-by: Dieter Nützel <[email protected]>
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Reviewed-by: Roland Scheidegger <[email protected]>
Tested-by: Dieter Nützel <[email protected]>
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Reviewed-by: Roland Scheidegger <[email protected]>
Tested-by: Dieter Nützel <[email protected]>
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This creates two new internal dependencies, idep_nir_headers and
idep_nir. The former encapsulates the generation of nir_opcodes.h and
nir_builder_opcodes.h and adding src/compiler/nir as an include path.
This ensures that any target that needs nir headers will have the
includes and that the generated headers will be generated before the
target is build. The second, idep_nir, includes the first and
additionally links to libnir.
This is intended to make it easier to avoid race conditions in the build
when using nir, since the number of consumers for libnir and it's
headers are quite high.
Acked-by: Eric Engestrom <[email protected]>
Signed-off-by: Dylan Baker <[email protected]>
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Signed-off-by: Rob Clark <[email protected]>
Reviewed-by: Roland Scheidegger <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Reviewed-by: Andres Rodriguez <[email protected]>
Reviewed-by: Wladimir J. van der Laan <[email protected]>
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This allow us to encapsulate the compiler and linkage requirements of
each driver in a reusable way. The result will be that each target that
needs a specific driver can simply add `driver_<name>` to its
dependencies line and the necessary libraries and compiler args will be
added. This will allow for a lot of code de-duplication between gallium
targets.
Signed-off-by: Dylan Baker <[email protected]>
Reviewed-by: Eric Engestrom <[email protected]>
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Since almost all BOs will be in one CL at a time, this cache will almost
always hit except for the first usage of the BO in each CL.
This didn't show up as statistically significant on the minetest trace
(n=340), but if I lop off the throttled lobe of the bimodal distribution,
it very clearly does (0.74731% +/- 0.162093%, n=269).
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No significant difference in the minetest replay, but it should reduce
overhead by not requiring that we write quad indices to index buffers that
we repeatedly re-upload (and making the draw packet smaller, as well).
Over the course of the series the actual game seems to be up by 1-2 fps.
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Now that there's only one user of it, it's pretty obvious how to avoid
emitting redundant ones. This should save a bunch of kernel validation
overhead.
No statistically sigificant difference on the minetest trace I was looking
at (n=169), but the maximum FPS is up by .3%
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Originally there was CL code for handling various relocations back when I
had relocs for the TSDA/TA buffers. Now that the kernel handles those
entirely on its own, I can inline that code into the one place using it.
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We failed to take the start into account for how many vertices to draw in
this round, so we would end up decrementing count below 0, which as an
unsigned number meant we would loop until the CLs soon ran out of space.
When I wrote the code I was thinking about how to use the previously
emitted shader state (no index bias baked into the elements) by emitting
up to 65535 and then only re-emitting with bias for the second wround, but
that doesn't work if the start is over 65535. Instead, just delay
emitting shader state until we get into the drawarrays GFXH-515 loop and
always bake the bias in when we're doing the workaround.
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For triangle strips, we step by max_verts - 2.
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(other uses of USE_VC4_SIMULATOR are already correct)
Signed-off-by: Eric Engestrom <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
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Stumbled into this when adding a new PIPE_CAP.
Signed-off-by: Andres Rodriguez <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
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This looks like an evergreen specific feature, but with atomic
counters AMD have hw specific counters they use instead of operating
on buffers directly. These are separate to the buffer atomics,
so require different limits and code paths.
I've left the CAP for atomic type extensible in case someone
else has a variant on this sort of thing (freedreno maybe?)
and needs to change it.
This adds all the CAPs required to add support for those atomic
counters, along with a related CAP for limiting the number of
output resources.
I'd like to land this and the st patch then I can start to
upstream the evergreen support for these and other GL4.x features.
v2: drop the ATOMIC_COUNTER_MODE cap, just use the return
from the HW counters. If 0 we use the current mode.
v3: fix some rebase errors (Gert Wollny)
Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Tested-By: Gert Wollny <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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This patch makes use of the DRM_IOCTL_VC4_GEM_MADVISE ioctl to mark all
BOs placed in the mesa BO cache as purgeable so that the system can
reclaim this memory under memory pressure.
v2:
- Removed BOs from the cache when they've been purged by the kernel
- Check whether the madvise ioctl is supported or not before using it
v3: Don't walk the whole list when we find a busy BO (by anholt, acked by
Boris)
Signed-off-by: Boris Brezillon <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
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Reviewed-by: Dylan Baker <[email protected]>
Reviewed-by: Eric Engestrom <[email protected]>
Tested-by: Timothy Arceri <[email protected]>
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Some hw (evergreen) has a limit on how many combined (images/buffers/mrts)
a fragment shader can access.
Reviewed-by: Ilia Mirkin <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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Mesa's DEBUG and assert's NDEBUG are not tied to each other, so we need
to explicitly compile this code out.
Fixes: 3df78928786134874eafa "vc4: Drop reloc_count tracking for debug
asserts on non-debug builds."
Cc: Eric Anholt <[email protected]>
Signed-off-by: Eric Engestrom <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
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This was causing Android clang version 3.8.256229 to miscompile,
presumably due to strict aliasing.
Fixes: 14dc281c1332 ("vc4: Enforce one-uniform-per-instruction after optimization.")
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It's redundant with nir_shader::info::stage.
Acked-by: Timothy Arceri <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>
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Reviewed-by: Dylan Baker <[email protected]>
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If there happened to be an ENOENT laying around, we would try using the
ioctls later and fail out resource allocation.
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It was calling down into i915 trying to label the BO, which is definitely
not the right thing.
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