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* vc4: Rewrite T image handling based on calling the LT handler.Eric Anholt2017-01-051-34/+75
* vc4: Move the utile_width/height functions to header inlines.Eric Anholt2017-01-052-37/+36
* vc4: Make the load/store utile functions static.Eric Anholt2017-01-052-4/+2
* vc4: Simplify the load/store utile functions.Eric Anholt2017-01-051-10/+22
* vc4: Reuse a list function to simplify bufmgr code.Eric Anholt2017-01-051-11/+2
* vc4: Flush the job early if we're referencing too many BOs.Eric Anholt2017-01-053-0/+16
* gallium: add PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELYMarek Olšák2017-01-051-0/+1
* nir: Rename convert_to_ssa lower_regs_to_ssaJason Ekstrand2016-12-291-1/+1
* vc4: Rework scheduling of thread switch to cut one more NOP.Eric Anholt2016-12-291-46/+75
* vc4: Fill thread switching delay slotsJonas Pfeil2016-12-291-7/+38
* vc4: Enable NIR-based loop unrolling.Eric Anholt2016-12-291-0/+5
* treewide: s/comparitor/comparator/Ilia Mirkin2016-12-121-1/+1
* gallium: support for native fence fd'sRob Clark2016-12-011-0/+1
* vc4: Avoid false scheduling dependencies for LOAD_IMMs.Eric Anholt2016-11-302-0/+9
* vc4: Try to schedule QIR instructions between writing to and reading math.Eric Anholt2016-11-301-0/+22
* vc4: Improve interleaving of texture coordinates vs results.Eric Anholt2016-11-301-3/+3
* vc4: Fix stray "." on no-op MUL packs.Eric Anholt2016-11-301-6/+6
* vc4: Allow merging instructions with SF set where the other writes NOP.Eric Anholt2016-11-301-0/+1
* vc4: In a loop break/continue, jump if everyone has taken the path.Eric Anholt2016-11-301-10/+17
* gallium: add PIPE_CAP_TGSI_CAN_READ_OUTPUTSNicolai Hähnle2016-11-301-0/+1
* vc4: Add a note for the future about texture latency calculation.Eric Anholt2016-11-291-0/+20
* vc4: Add support for coalescing ALU ops into tex_[srtb] MOVs.Eric Anholt2016-11-294-29/+37
* vc4: Restructure VPM write optimization into two passes.Eric Anholt2016-11-291-18/+10
* vc4: Make qir_for_each_inst_inorder() safe against removal.Eric Anholt2016-11-291-1/+1
* vc4: Split optimizing VPM writes from VPM reads.Eric Anholt2016-11-295-51/+110
* vc4: Restructure texture insts as ALU ops with tex_[strb] as the dst.Eric Anholt2016-11-299-89/+194
* vc4: Refactor qir_get_op_nsrc(enum qop) to qir_get_nsrc(struct qinst *).Eric Anholt2016-11-2917-36/+34
* vc4: Replace the qinst src[] with a fixed-size array.Eric Anholt2016-11-293-4/+2
* vc4: Remove qir_inst4().Eric Anholt2016-11-292-25/+0
* vc4: Don't conditionalize the src1 mov of qir_SEL().Eric Anholt2016-11-221-4/+2
* vc4: Re-add R4 to the "any" register class.Eric Anholt2016-11-221-0/+2
* vc4: Disable MSAA rasterization when the job binning is single-sampled.Eric Anholt2016-11-221-2/+13
* vc4: Make sure we don't overflow texture input/output FIFOs when threaded.Eric Anholt2016-11-221-2/+3
* gallium: fix more occurences of u_hash.hMarek Olšák2016-11-221-1/+1
* vc4: Try compiling our FSes in multithreaded mode on new kernels.Eric Anholt2016-11-165-2/+20
* vc4: Add support for ETC1 textures if the kernel is new enough.Eric Anholt2016-11-164-5/+18
* vc4: Fix simulator mode missing-GETPARAM debug info.Eric Anholt2016-11-161-1/+1
* vc4: Fix resource leak in register allocation failure path.Mun Gwan-gyeong2016-11-161-0/+2
* gallium: add PIPE_SHADER_CAP_LOWER_IF_THRESHOLDMarek Olšák2016-11-151-0/+1
* vc4: Add simulator kernel validation for multithreaded fragment shaders.Jonas Pfeil2016-11-123-5/+76
* vc4: Mark threaded FSes as non-singlethread in the CL.Eric Anholt2016-11-123-1/+6
* vc4: Flag the last thread switch in the program as the last.Eric Anholt2016-11-123-0/+34
* vc4: Add THRSW nodes after each tex sample setup in multithreaded mode.Eric Anholt2016-11-122-0/+49
* vc4: Add some spec citations about texture fifo management.Eric Anholt2016-11-121-5/+37
* vc4: Use ra14/rb14 as the spilling registers.Eric Anholt2016-11-122-8/+8
* vc4: Add support for register allocation for threaded shaders.Eric Anholt2016-11-123-20/+85
* vc4: Split register class setup for physical files from accumulators.Eric Anholt2016-11-121-17/+19
* vc4: Use register allocator CLASS_BIT_R0_R3 to clean up CLASS_B.Eric Anholt2016-11-121-4/+4
* vc4: Add support for QPU scheduling of thread switch instructions.Eric Anholt2016-11-121-2/+27
* vc4: Add a thread switch QIR instruction.Eric Anholt2016-11-123-0/+18
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